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"A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor."

Jürgen Pille et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433849

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-05

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  - conf/isscc/PilleWWSPFBTEPHRC10
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  - https://dblp.org/rec/conf/isscc/PilleWWSPFBTEPHRC10
Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles G. Canada:
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. ISSCC 2010: 344-345

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