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"A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache."

John Barth et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433814

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-16

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John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, Nianzheng Cao:
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. ISSCC 2010: 342-343

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