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Hiroyuki Igura
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2010 – 2019
- 2012
- [c3]Toshiki Takeuchi, Hiroyuki Igura, Masao Ikekawa:
Stream-access-oriented baseband signal processors for SDR. ISCAS 2012: 1795-1798
2000 – 2009
- 2005
- [c2]Toshiki Takeuchi, Hiroyuki Igura, Takeshi Hashimoto, Soichi Tsumura, Naoki Nishi:
Scalable bus interface for HSDPA co-processor extension. CICC 2005: 51-54 - 2002
- [c1]Hiroyuki Igura, Masaru Hirata, Junya Yamada, Masakazu Yamashina, Shigeru Ono:
A low-power W-CDMA demodulator using specially-designed micro-DSPs. CICC 2002: 397-400
1990 – 1999
- 1998
- [j4]Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura
, Masakazu Yamashina:
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits 33(11): 1820-1828 (1998) - 1997
- [j3]Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina:
A 0.25-μm CMOS 0.9-V 100-MHz DSP core. IEEE J. Solid State Circuits 32(1): 52-61 (1997) - 1996
- [j2]Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada:
A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits 31(6): 784-791 (1996) - 1994
- [j1]Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada:
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits 29(12): 1464-1473 (1994)
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