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ORCIDRiichiro Takemura
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2010 – 2019
- 2012
[j11]Akira Kotabe, Kiyoo Itoh, Riichiro Takemura:
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Trans. Electron. 95-C(4): 555-563 (2012)- [j10]Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh:
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. 95-C(4): 594-599 (2012) - [j9]Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh:
A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. IEICE Trans. Electron. 95-C(4): 600-608 (2012) - [j8]Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
:
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. 95-C(4): 651-660 (2012) - [j7]Takayuki Kawahara, Kenchi Ito, Riichiro Takemura, Hideo Ohno:
Spin-transfer torque RAM technology: Review and prospect. Microelectron. Reliab. 52(4): 613-627 (2012) - [c9]Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara:
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS 2012: 2299-2302 - 2011
- [c8]Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7 - 2010
- [j6]Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno:
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45(4): 869-879 (2010)
2000 – 2009
- 2009
- [c7]Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh:
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC 2009: 142-143 - 2008
- [j5]Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno:
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits 43(1): 109-120 (2008) - 2007
- [j4]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara:
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. 90-C(4): 758-764 (2007) - [c6]Kiyoo Itoh, Riichiro Takemura:
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. ICECS 2007: 739-742 - [c5]Takayuki Kawahara, Riichiro Takemura, Hiromasa Takahashi, Hideo Ohno:
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS 2007: 1011-1014 - [c4]Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno:
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC 2007: 480-617 - 2006
- [j3]Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara:
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits 41(1): 107-112 (2006) - [c3]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi:
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. ISLPED 2006: 123-126 - 2005
- [j2]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara:
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits 40(4): 853-861 (2005) - [c2]Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa:
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC 2005: 431-434 - [c1]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara:
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC 2005: 1048-1052 - 2001
- [j1]Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36(11): 1721-1727 (2001)
Coauthor Index
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