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ORCIDAxel Jantsch
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Publications
- 2017
[e5]Axel Jantsch, Hiroki Matsutani, Zhonghai Lu, Ümit Y. Ogras:
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Republic of Korea, October 19 - 20, 2017. ACM 2017, ISBN 978-1-4503-4984-0 [contents]- 2016
- [j52]Fahimeh Jafari
, Axel Jantsch, Zhonghai Lu:
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3387-3400 (2016) - 2015
- [j49]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen:
Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications. J. Electr. Comput. Eng. 2015: 902591:1-902591:20 (2015) - [j48]Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels. J. Syst. Archit. 61(9): 423-434 (2015) - [j47]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Shenggang Chen, Hu Chen, Man Liao:
Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips. J. Softw. 10(2): 142-161 (2015) - [j45]Fahimeh Jafari, Zhonghai Lu, Axel Jantsch:
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels. ACM Trans. Design Autom. Electr. Syst. 20(3): 35:1-35:33 (2015) - [c148]Chaochao Feng, Zhuofan Liao, Zhonghai Lu, Axel Jantsch, Zhenyu Zhao:
Performance analysis of on-chip bufferless router with multi-ejection ports. ASICON 2015: 1-4 - [c147]Yuang Zhang, Li Li, Axel Jantsch, Zhonghai Lu, Minglun Gao, Yuxiang Fu, Hongbing Pan:
Exploring stacked main memory architecture for 3D GPGPUs. ASICON 2015: 1-4 - [c141]Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen:
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. ISVLSI 2015: 398-403 - [c139]Shaoteng Liu, Zhonghai Lu, Axel Jantsch:
Highway in TDM NoCs. NOCS 2015: 15:1-15:8 - 2014
- [j43]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Yang Guo, Hengzhu Liu:
Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs. IEICE Electron. Express 11(18): 20140542 (2014) - [j42]Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Minglun Gao, Hongbing Pan, Feng Han:
A survey of memory architecture for 3D chip multi-processors. Microprocess. Microsystems 38(5): 415-430 (2014) - [j41]Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2229-2233 (2014) - [c135]Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Parallel probe based dynamic connection setup in TDM NoCs. DATE 2014: 1-6 - [c132]Yuang Zhang, Li Li, Zhonghai Lu, Axel Jantsch, Yuxiang Fu, Minglun Gao:
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips. ISCAS 2014: 1961-1964 - 2013
- [j40]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Shenggang Chen, Huitao Gu:
Reducing Virtual-to-Physical address translation overhead in Distributed Shared Memory based multi-core Network-on-Chips according to data property. Comput. Electr. Eng. 39(2): 596-612 (2013) - [j39]Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu:
Mathematical formalisms for performance evaluation of networks-on-chip. ACM Comput. Surv. 45(3): 38:1-38:41 (2013) - [j37]Abdul Naeem, Axel Jantsch, Zhonghai Lu:
Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 760-773 (2013) - [j36]Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch:
An Analytical Latency Model for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 113-123 (2013) - [j35]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing:
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1053-1066 (2013) - [c130]Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC. DSD 2013: 21-28 - [c129]Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch:
Efficient distributed memory management in a multi-core H.264 decoder on FPGA. ISSoC 2013: 1-4 - 2012
- [j34]Wenmin Hu, Hengzhu Liu, Zhonghai Lu, Axel Jantsch, Guitao Fu:
Self-selection pseudo- circuit: a clever crossbar pre-allocation. IEICE Electron. Express 9(6): 558-564 (2012) - [j33]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Xianju Yang:
Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. IEICE Trans. Inf. Syst. 95-D(4): 1052-1061 (2012) - [j32]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip. IEICE Trans. Inf. Syst. 95-D(5): 1519-1522 (2012) - [j31]Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng:
Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks. Int. J. Distributed Sens. Networks 8 (2012) - [j30]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
A Survey of FPGA Dynamic Reconfiguration Design Methodology and Applications. Int. J. Embed. Real Time Commun. Syst. 3(2): 23-39 (2012) - [j29]Wenmin Hu, Zhonghai Lu, Hengzhu Liu, Axel Jantsch:
TPSS: A Flexible Hardware Support for Unicast and Multicast on Network-on-Chip. J. Comput. 7(7): 1743-1752 (2012) - [c127]Abbas Eslami Kiasari, Axel Jantsch, Marco Bekooij, Alan Burns, Zhonghai Lu:
Analytical approaches for performance evaluation of networks-on-chip. CASES 2012: 211-212 - [c126]Fahimeh Jafari, Axel Jantsch, Zhonghai Lu:
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling. DATE 2012: 538-541 - [c125]Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC. DATE 2012: 1289-1294 - [c124]Abdul Naeem, Axel Jantsch, Zhonghai Lu:
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems. DSD 2012: 304-311 - [c123]Abdul Naeem, Axel Jantsch, Zhonghai Lu:
Scalability analysis of release and sequential consistency models in NoC based multicore systems. ISSoC 2012: 1-7 - [c122]Huimin She, Zhonghai Lu, Axel Jantsch:
System-level evaluation of sensor networks deployment strategies: Coverage, lifetime and cost. IWCMC 2012: 549-554 - 2011
- [j27]Ming Liu, Wolfgang Kuehn, S. Lange, Shuo Yang, J. Roskoss, Zhonghai Lu, Axel Jantsch, Qiang Wang, Hao Xu, Dapeng Jin:
A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments. Comput. Sci. Eng. 13(2): 52-63 (2011) - [j26]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
FPGA-Based Particle Recognition in the HADES Experiment. IEEE Des. Test Comput. 28(4): 48-57 (2011) - [j25]Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Zhonghai Lu, Dimitrios Soudris, Axel Jantsch:
Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations. IEEE Embed. Syst. Lett. 3(2): 66-69 (2011) - [j24]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Hai Liu:
Cooperative communication based barrier synchronization in on-chip mesh architectures. IEICE Electron. Express 8(22): 1856-1862 (2011) - [j23]Xiaowen Chen, Shuming Chen, Zhonghai Lu, Axel Jantsch:
Hybrid Distributed Shared Memory Space in Multi-core Processors. J. Softw. 6(12): 2369-2378 (2011) - [c120]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments. ARC 2011: 169-180 - [c119]Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang:
Evaluation of deflection routing on various NoC topologies. ASICON 2011: 163-166 - [c118]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems. ASP-DAC 2011: 154-159 - [c117]Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu:
Power-efficient tree-based multicast support for Networks-on-Chip. ASP-DAC 2011: 363-368 - [c116]Abdul Naeem, Axel Jantsch, Xiaowen Chen, Zhonghai Lu:
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems. DSD 2011: 47-54 - [c114]Fahimeh Jafari, Axel Jantsch, Zhonghai Lu:
Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling. ICCD 2011: 445-446 - [c113]Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch:
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. ISVLSI 2011: 19-24 - [c111]Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng:
Stochastic coverage in event-driven sensor networks. PIMRC 2011: 915-919 - [c109]Wenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu:
Network-on-Chip multicasting with low latency path setup. VLSI-SoC 2011: 290-295 - [c107]Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng:
Modeling and analysis of Rayleigh fading channels using stochastic network calculus. WCNC 2011: 1056-1061 - 2010
- [j21]Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee:
Buffer Optimization in Network-on-Chip Through Flow Regulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1973-1986 (2010) - [c105]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. DATE 2010: 39-44 - [c104]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
FPGA-based adaptive computing for correlated multi-stream processing. DATE 2010: 973-976 - [c102]Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee:
Optimal regulation of traffic flows in networks-on-chip. DATE 2010: 1621-1624 - [c99]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Scalability of weak consistency in NoC based multicore architectures. ISCAS 2010: 3497-3500 - [c98]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing. ISVLSI 2010: 80-85 - [c97]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
The MOSART Mapping Optimization for Multi-Core ARchiTectures. ISVLSI (Selected papers) 2010: 181-195 - [c96]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu:
Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique. ISVLSI 2010: 462-463 - [c95]Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI 2010: 518-523 - [c94]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang:
A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip. NoCArc@MICRO 2010: 11-16 - [c93]Abbas Eslami Kiasari, Axel Jantsch, Zhonghai Lu:
A framework for designing congestion-aware deterministic routing. NoCArc@MICRO 2010: 45-50 - [c91]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Run-Time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips. PAAP 2010: 39-46 - [c90]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations. ReCoSoC 2010: 149-152 - [c89]Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang:
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. SoCC 2010: 441-446 - [c88]Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory. SoCC 2010: 467-472 - 2009
- [j20]Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jantsch:
Scalability of relaxed consistency models in NoC based multicore architectures. SIGARCH Comput. Archit. News 37(5): 8-15 (2009) - [c87]Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen:
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC 2009: 1-7 - [c86]Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson:
Flow regulation for on-chip communication. DATE 2009: 578-581 - [c83]Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch:
Run-time Partial Reconfiguration speed investigation and architectural design space exploration. FPL 2009: 498-502 - [c81]Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen:
Scalability of network-on-chip communication architecture for 3-D meshes. NOCS 2009: 114-123 - [c80]Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Shuo Yang, Axel Jantsch:
A Reconfigurable Design Framework for FPGA Adaptive Computing. ReConFig 2009: 439-444 - [c79]Zhonghai Lu, Dimitris Brachos, Axel Jantsch:
A flow regulator for On-Chip Communication. SoCC 2009: 151-154 - [c78]Huimin She, Zhonghai Lu, Axel Jantsch, Dian Zhou, Li-Rong Zheng:
Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. VTC Spring 2009 - 2008
- [j13]Zhonghai Lu, Axel Jantsch:
TDM Virtual-Circuit Configuration for Network-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 1021-1034 (2008) - [c76]Zhonghai Lu, Lei Xia, Axel Jantsch:
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. DDECS 2008: 92-97 - [c75]Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch:
System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. DSD 2008: 599-605 - [c72]Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch:
ATCA-based computation platform for data acquisition and triggering in particle physics experiments. FPL 2008: 287-292 - 2007
- [j11]Zhonghai Lu, Axel Jantsch:
Admitting and ejecting flits in wormhole-switched networks on chip. IET Comput. Digit. Tech. 1(5): 546-556 (2007) - [c69]Zhonghai Lu, Ming Liu, Axel Jantsch:
Layered Switching for Networks on Chip. DAC 2007: 122-127 - [c66]Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou:
Traffic Splitting with Network Calculus for Mesh Sensor Networks. FGCN (2) 2007: 368-373 - [c64]Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez, Zhen'An Liu:
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics. FPT 2007: 177-183 - [c62]Zhonghai Lu, Axel Jantsch:
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. ICCAD 2007: 18-25 - [c58]Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch:
Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping 2007: 143-149 - 2006
- [c52]Zhonghai Lu, Ingo Sander, Axel Jantsch:
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. DSD 2006: 37-44 - [c48]Zhonghai Lu, Mingchen Zhong, Axel Jantsch:
Evaluation of on-chip networks using deflection routing. ACM Great Lakes Symposium on VLSI 2006: 296-301 - [c47]Zhonghai Lu, Bei Yin, Axel Jantsch:
Connection-oriented Multicasting in Wormhole-switched Networks on Chip. ISVLSI 2006: 205-210 - 2005
- [c44]Zhonghai Lu, Axel Jantsch, Ingo Sander:
Feasibility analysis of messages for on-chip networks using wormhole routing. ASP-DAC 2005: 960-964 - [c42]Zhonghai Lu, Ingo Sander, Axel Jantsch:
Refinement of Perfectly Synchronous Communication Model. FDL 2005: 453-465 - [c39]Zhonghai Lu, Axel Jantsch:
Traffic Configuration for Evaluating Networks on Chips. IWSOC 2005: 535-540 - 2004
- [c34]Zhonghai Lu, Axel Jantsch:
Flit admission in on-chip wormhole-switched networks with virtual channels. SoC 2004: 21-24 - 2003
- [c30]Ingo Sander, Axel Jantsch, Zhonghai Lu:
Development and Application of Design Transformations in ForSyDe. DATE 2003: 10364-10369 - 2002
- [c21]Ingo Sander, Axel Jantsch, Zhonghai Lu:
A Case Study of Hardware and Software Synthesis in ForSyDe. ISSS 2002: 86-91
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