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ORCID5th ReCoSoC 2010, Karlsruhe, Germany
- Michael Hübner, Loïc Lagadec, Oliver Sander, Jürgen Becker:
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010. KIT Scientific Reports 7551, KIT Scientific Publishing 2010, ISBN 978-3-86644-515-4
Session 1: Multiprocessor System on Chip
- Rémi Busseuil, Gabriel Marchesan Almeida, Sameer Varyani, Pascal Benoit, Gilles Sassatelli:
A Self-adaptive communication protocol allowing fine tuning between flexibility and performance in Homogeneous MPSoC systems. ReCoSoC 2010: 1-5 - Leandro Möller, André Rodrigues, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner:
Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. ReCoSoC 2010: 7-11 - Diana Goehringer, Jonathan Obie, Michael Hübner, Jürgen Becker:
Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors. ReCoSoC 2010: 13-20
Session 2: Design-optimization of Reconfigurable Systems
- Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid:
Novel Approach for Modeling Very Dynamic and Flexible Real Time Applications. ReCoSoC 2010: 21-27 - Ikbel Belaid, Fabrice Muller, Maher Benjemaa:
New Three-level Resource Management for Off-line Placement of Hardware Tasks on Reconfigurable Devices. ReCoSoC 2010: 29-36 - Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez:
Exploration of Heterogeneous FPGA Architectures. ReCoSoC 2010: 37-44
Session 3: Self-Adaptive Reconfigurable System
- Christian Schuck, Bastian Haetzer, Jürgen Becker:
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. ReCoSoC 2010: 45-50 - Stefan Döbrich, Christian Hochberger:
Practical Resource Constraints for Online Synthesis. ReCoSoC 2010: 51-58 - Florian Thoma, Jürgen Becker:
ISRC: a runtime system for heterogeneous reconfigurable architectures. ReCoSoC 2010: 59-65
Session 4: Fault Tolerant Systems
- Mohsin Amin, Camille Diou, Fabrice Monteiro, Abbas Ramazani, Abbas Dandache:
A Self-Checking HW Journal for a Fault Tolerant Processor Architecture. ReCoSoC 2010: 67-71 - Onur Derin, Erkan Diken:
A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip. ReCoSoC 2010: 73-78 - Monica Magalhães Pereira, Luigi Carro:
Dynamic Reconfigurable Computing: the Alternative to Homogeneous Multicores under Massive Defect Rates. ReCoSoC 2010: 79-86
Session 5: Analysis of FPGA Architectures
- Nachiket Kapre, André DeHon:
An NoC Traffic Compiler for efficient FPGA implementation of Parallel Graph Applications. ReCoSoC 2010: 87-94 - Florent Bruguier, Pascal Benoit, Lionel Torres:
Investigation of Digital Sensors for Variability Characterization on FPGAs. ReCoSoC 2010: 95-100 - Markus Ferringer:
Investigating Self-Timed Circuits for the Time-Triggered Protocol. ReCoSoC 2010: 101-108 - Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker:
First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography. ReCoSoC 2010: 109-114
Session 6: Security on Reconfigurable Systems
- Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker:
ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded Systems. ReCoSoC 2010: 115-120 - Alexander Klimm, Benjamin Glas, Matthias Wachs, Jürgen Becker, Klaus D. Müller-Glaser:
A Secure Keyflashing Framework for Access Systems in Highly Mobile Devices. ReCoSoC 2010: 121-126
Session 7: Reconfigurable Computing and Reconfigurable Education Special
- Loïc Lagadec, Damien Picard, Pierre-Yves Lucas:
Session Teaching Reconfigurable Processor: the Biniou Approach. ReCoSoC 2010: 127-134 - Cédric Killian, Camel Tanougast, M. Monteiro, Camille Diou, Abbas Dandache, Slavisa Jovanovic:
Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education. ReCoSoC 2010: 135-139 - Jean-Baptiste Rigaud, Jean-Max Dutertre, Michel Agoyan, Bruno Robisson, Assia Tria:
Experimental Fault Injection based on the Prototyping of an AES Cryptosystem. ReCoSoC 2010: 141-147
Poster Session
- Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations. ReCoSoC 2010: 149-152 - Roberto Airoldi, Fabio Garzia, Jari Nurmi:
Timing Synchronization for a Multi-Standard Receiver on a Multi-Processor System-onChip. ReCoSoC 2010: 153-155 - Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC 2010: 157-160 - Joachim Knäblein, Claudia Tischendorf, Erik Markert, Ulrich Heinkel:
Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validation. ReCoSoC 2010: 161-168 - Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa:
A New Client Interface Architecture for the Modified Fat Tree (MFT) Network-on-Chip (NoC) Topology. ReCoSoC 2010: 169-172 - Fabio Garzia, Roberto Airoldi, Jari Nurmi:
Implementation of Conditional Execution on a Coarse-Grain Reconfigurable Array. ReCoSoC 2010: 173-174 - Omer Kilic, Peter Lee:
Dynamically Reconfigurable Architectures for High Speed Vision Systems. ReCoSoC 2010: 175-177 - Ludovic Barrandon, Thierry Capitaine, Loïc Lagadec, Nathalie Julien, Christophe Moy, Thierry Monédière:
Virtual SoPC rad-hardening for satellite applications. ReCoSoC 2010: 179-180
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