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2020 – today
- 2024
[j19]Miguel Reis
, Mário P. Véstias, Horácio C. Neto:
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines. ACM Trans. Reconfigurable Technol. Syst. 17(1): 6:1-6:30 (2024)- [c58]Henrique B. Brum, Mário P. Véstias, Horácio C. Neto:
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization. ARC 2024: 90-105 - [c57]José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias:
PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH 2024: 139-146 - 2023
- [j18]Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte:
Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA. Algorithms 16(3): 141 (2023) - [j17]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. 16(1): 13:1-13:36 (2023) - 2022
- [j16]Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte:
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective. Remote. Sens. 14(5): 1258 (2022) - [j15]Francisco Melo, Horácio C. Neto, Hugo Plácido da Silva:
System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics. Sensors 22(1): 348 (2022) - [j14]David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 15: 3600-3611 (2022) - 2021
- [j13]Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access 9: 75864-75877 (2021) - [j12]Mário P. Véstias, Horácio C. Neto:
Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms 14(7): 198 (2021) - [j11]Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa:
Configurable Hardware Core for IoT Object Detection. Future Internet 13(11): 280 (2021) - 2020
- [j10]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access 8: 107229-107243 (2020) - [j9]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Moving Deep Learning to the Edge. Algorithms 13(5): 125 (2020) - [j8]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems 77: 103136 (2020) - [c56]Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto:
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm. ARC 2020: 392-401
2010 – 2019
- 2019
- [j7]João Vieira, Rui Policarpo Duarte, Horácio C. Neto:
kNN-STUFF: kNN STreaming Unit for Fpgas. IEEE Access 7: 170864-170877 (2019) - [j6]Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto:
Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection. J. Aerosp. Inf. Syst. 16(11): 512-520 (2019) - [c55]Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto:
Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. ARC 2019: 3-16 - [c54]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL 2019: 350-353 - 2018
- [j5]Mário P. Véstias, Horácio C. Neto:
Improving the area of fast parallel decimal multipliers. Microprocess. Microsystems 61: 96-107 (2018) - [c53]Rui Policarpo Duarte, Horácio C. Neto:
Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems. DSC 2018: 1-8 - [c52]Luís Fiolhais, Horácio C. Neto:
An Efficient Exact Fused Dot Product Processor in FPGA. FPL 2018: 327-330 - [c51]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL 2018: 399-402 - [c50]Rui Policarpo Duarte, Álvaro Simões, Rui Henriques, Horácio C. Neto:
FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering. PBio@EuroMPI 2018: 53-62 - 2017
- [j4]Horácio C. Neto, Mário P. Véstias:
Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems 55: 91-99 (2017) - [c49]João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias:
K-means clustering on CGRA. FPL 2017: 1-4 - [c48]Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto:
Parallel dot-products for deep learning on FPGA. FPL 2017: 1-4 - 2016
- [c47]Jose Canilho, Mário P. Véstias, Horácio C. Neto:
Multi-core for K-means clustering on FPGA. FPL 2016: 1-4 - [c46]Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias:
XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system. ICRC 2016: 1-7 - 2015
- [c45]João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias:
Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture. DSD 2015: 330-336 - [c44]Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra:
Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions. FCCM 2015: 256-259 - [c43]Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto:
Enhancing stochastic computations via process variation. FPL 2015: 1-7 - [c42]Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra:
A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow. ISVLSI 2015: 161-166 - [c41]Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra:
FPGA redundancy recovery based on partial bitstreams for multiple partitions. LATS 2015: 1-4 - [i2]Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto:
Designing Hardware/Software Systems for Embedded High-Performance Computing. CoRR abs/1508.06832 (2015) - 2014
- [c40]Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias:
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA. FPL 2014: 1-4 - [c39]Mário P. Véstias, Horácio C. Neto:
Trends of CPU, GPU and FPGA for high-performance computing. FPL 2014: 1-6 - [i1]Mário P. Véstias, Horácio C. Neto:
A Many-Core Overlay for High-Performance Embedded Computing on FPGAs. CoRR abs/1408.5401 (2014) - 2013
- [c38]Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias:
Analysis of matrix multiplication on high density Virtex-7 FPGA. FPL 2013: 1-4 - [c37]Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
A reconfigurable computing architecture using magnetic tunneling junction memories. FPL 2013: 1-2 - [c36]Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto:
Design of a massively parallel computing architecture for dense matrix multiplication. LASCAS 2013: 1-4 - [c35]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of a multiband full-rate ultra-wideband receiver in FPGA. LASCAS 2013: 1-4 - [c34]Horácio C. Neto, Mário P. Véstias:
Very low resource table-based FPGA evaluation of elementary functions. ReConFig 2013: 1-6 - 2012
- [c33]Mário P. Véstias, Horácio C. Neto:
Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm. DSD 2012: 782-788 - [c32]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs. DSD 2012: 938-945 - [c31]Mário P. Véstias, Horácio C. Neto, Helena Sarmento:
Sliding block Viterbi decoders in FPGA. FPL 2012: 595-598 - [c30]Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes:
Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions. ICECS 2012: 809-812 - [c29]Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory. ReConFig 2012: 1-6 - 2011
- [c28]Mário P. Véstias, Horácio C. Neto:
Revisiting the Newton-Raphson Iterative Method for Decimal Division. FPL 2011: 138-143 - 2010
- [c27]Victor Silva, Jorge R. Fernandes, Horácio C. Neto:
Reconfigurable Circuits Using Magnetic Tunneling Junction Memories. DoCEIS 2010: 549-558
2000 – 2009
- 2009
- [c26]Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto:
Run-Time Reconfigurable Array Using Magnetic RAM. DSD 2009: 74-81 - [c25]Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias:
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. DSD 2009: 273-280 - [c24]Rui Marcelino, Horácio C. Neto, João M. P. Cardoso:
Unbalanced FIFO sorting for FPGA-based systems. ICECS 2009: 431-434 - 2008
- [c23]Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto:
Multiplier-based double precision floating point divider according to the IEEE-754 standard. ARC 2008: 260-265 - [c22]Horácio C. Neto, Mário P. Véstias:
Decimal multiplier on FPGA using embedded binary multipliers. FPL 2008: 197-202 - [c21]Rui Marcelino, Horácio C. Neto, João M. P. Cardoso:
Sorting Units for FPGA-Based Embedded Systems. DIPES 2008: 11-22 - 2007
- [c20]Mário P. Véstias, Horácio C. Neto:
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems. FPL 2007: 389-394 - 2006
- [c19]Mário P. Véstias, Horácio C. Neto:
Area/Performance Improvement of NoC Architectures. ARC 2006: 193-198 - [c18]Mário P. Véstias, Horácio C. Neto:
Co-synthesis of a configurable SoC platform based on a network on chip architecture. ASP-DAC 2006: 48-53 - [c17]Goncalo M. de Matos, Horácio C. Neto:
On Reconfigurable Architectures for Efficient Matrix Inversion. FPL 2006: 1-6 - [c16]Mário P. Véstias, Horácio C. Neto:
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. FPL 2006: 1-4 - [c15]Mário P. Véstias, Horácio C. Neto:
Area and performance optimization of a generic network-on-chip architecture. SBCCI 2006: 68-73 - 2005
- [c14]Pedro M. Domingos, Fernando M. Silva, Horácio C. Neto:
An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. FPL 2005: 89-94 - [c13]Ricardo S. Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto:
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping. SAMOS 2005: 41-50 - 2004
- [c12]Ricardo S. Ferreira, João M. P. Cardoso, Horácio C. Neto:
An Environment for Exploring Data-Driven Architectures. FPL 2004: 1022-1026 - 2003
- [j3]João M. P. Cardoso, Horácio C. Neto:
Compilation for FPGA-Based Reconfigurable Hardware. IEEE Des. Test Comput. 20(2): 65-75 (2003) - [c11]Mário P. Véstias, Horácio C. Neto:
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. SBCCI 2003: 85- - 2002
- [c10]Mário P. Véstias, Horácio C. Neto:
System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures. IEEE International Workshop on Rapid System Prototyping 2002: 130-137 - 2001
- [j2]Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
An exact solution to the minimum size test pattern problem. ACM Trans. Design Autom. Electr. Syst. 6(4): 629-644 (2001) - [c9]João M. P. Cardoso, Horácio C. Neto:
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. FPL 2001: 523-533
1990 – 1999
- 1999
- [c8]João M. P. Cardoso, Horácio C. Neto:
Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System. FCCM 1999: 2-11 - [c7]Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
On Applying Set Covering Models to Test Set Compaction. Great Lakes Symposium on VLSI 1999: 8-11 - [c6]João M. P. Cardoso, Horácio C. Neto:
An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. VLSI 1999: 485-496 - [c5]Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva:
Test pattern generation for width compression in BIST. ISCAS (1) 1999: 114-118 - [c4]Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva:
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. VLSI Design 1999: 37-41 - 1998
- [c3]Paulo F. Flores, Horácio C. Neto, João P. Marques Silva:
An exact solution to the minimum size test pattern problem. ICCD 1998: 510-515 - [c2]João M. P. Cardoso, Horácio C. Neto:
Towards an automatic path from JavaTM bytecodes to hardware through high-level synthesis. ICECS 1998: 85-88 - 1994
- [c1]José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto:
Bitwise Encoding of Finite State Machines. VLSI Design 1994: 379-382 - 1992
- [j1]Luís Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal:
On exponential fitting for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 566-574 (1992)
Coauthor Index
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last updated on 2024-07-18 21:56 CEST by the dblp team
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