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"Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor."

Mário P. Véstias, Horácio C. Neto (2021)

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DOI: 10.3390/A14070198

access: open

type: Journal Article

metadata version: 2023-08-28

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  dblp key:
  - journals/algorithms/VestiasN21
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  - https://dblp.org/rec/journals/algorithms/VestiasN21
Mário P. Véstias, Horácio C. Neto:
Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. Algorithms 14(7): 198 (2021)

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