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"Decimal addition on FPGA based on a mixed BCD/excess-6 representation."

Horácio C. Neto, Mário P. Véstias (2017)

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DOI: 10.1016/J.MICPRO.2017.10.004

access: closed

type: Journal Article

metadata version: 2022-12-07

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Horácio C. Neto, Mário P. Véstias:
Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems 55: 91-99 (2017)

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