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15th ARC 2019: Darmstadt, Germany
- Christian Hochberger, Brent Nelson, Andreas Koch, Roger F. Woods, Pedro C. Diniz:
Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings. Lecture Notes in Computer Science 11444, Springer 2019, ISBN 978-3-030-17226-8
Applications
- Helena Cruz
, Rui Policarpo Duarte
, Horácio C. Neto
:
Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging. 3-16 - Shuanglong Liu
, Ringo S. W. Chu, Xiwei Wang, Wayne Luk:
Optimizing CNN-Based Hyperspectral Image Classification on FPGAs. 17-31 - Johan Peltenburg, Jeroen van Straten
, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars:
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow. 32-47 - Günter Knittel:
A Novel Encoder for TDCs. 48-57 - Qian Zhao
, Yoshimasa Ohnishi
, Masahiro Iida
, Takaichi Yoshida
:
A Resource Reduced Application-Specific FPGA Switch. 58-67 - Panagiotis G. Mousouliotis
, Loukas P. Petrou
:
Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications. 68-77
Partial Reconfiguration and Security
- Bruno da Silva
, An Braeken
, Abdellah Touhafi
:
Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling. 81-95 - Tobias Dörr
, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker:
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems. 96-111 - Kenneth Schmitz
, Buse Ustaoglu
, Daniel Große
, Rolf Drechsler
:
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. 112-126 - Qazi Arbab Ahmed
, Tobias Wiersema
, Marco Platzner
:
Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. 127-136 - Nadir Khan
, Arthur Silitonga
, Brian Pachideh, Sven Nitzsche
, Jürgen Becker
:
Secure Local Configuration of Intellectual Property Without a Trusted Third Party. 137-146
Image/Video Processing
- Lester Kalms
, Ariel Podlubne
, Diana Göhringer
:
HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing. 149-164 - Piotr Ciarach, Marcin Kowalczyk
, Dominika Przewlocka
, Tomasz Kryjak
:
Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream. 165-180 - Konstantinos Boikos
, Christos-Savvas Bouganis
:
A Scalable FPGA-Based Architecture for Depth Estimation in SLAM. 181-196
High-Level Synthesis
- Zheming Jin
, Hal Finkel
:
Evaluating LULESH Kernels on OpenCL FPGA. 199-213 - Jens Korinth
, Jaco A. Hofmann
, Carsten Heinz
, Andreas Koch
:
The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems. 214-229 - Afonso Canas Ferreira
, João M. P. Cardoso
:
Graph-Based Code Restructuring Targeting HLS for FPGAs. 230-244
CGRAs and Vector Processing
- Dennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel, Andreas Koch:
UltraSynth: Integration of a CGRA into a Control Engineering Environment. 247-261 - João Paulo C. de Lima, Paulo C. Santos, Rafael Fao de Moura, Marco A. Z. Alves
, Antonio C. S. Beck, Luigi Carro:
Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories. 262-276 - André Werner
, Florian Fricke
, Keyvan Shahin
, Florian Werner
, Michael Hübner
:
Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms. 277-291
Architectures
- Ludovica Bozzoli
, Luca Sterpone
:
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures. 295-304 - Johanna Rohde
, Lukas Johannes Jung, Christian Hochberger:
Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators. 305-316
Design Frameworks and Methodology
- Leonard Masing, Fabian Lesniak, Jürgen Becker:
Hybrid Prototyping for Manycore Design and Validation. 319-333 - Umar Ibrahim Minhas
, Roger F. Woods
, Georgios Karakonstantis:
Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks. 334-349
Invited Talk
- Brent E. Nelson
:
Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape. 353-367
Convolutional Neural Networks
- Masayuki Shimoda, Youki Sada, Hiroki Nakahara
:
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation. 371-386 - Ana Gonçalves
, Tiago Peres
, Mário P. Véstias
:
Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs. 387-401 - Tiago Peres
, Ana Gonçalves
, Mário P. Véstias
:
Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning. 402-416
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