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ORCIDH.-S. Philip Wong
Hon-Sum Philip Wong
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- affiliation: Stanford University, USA
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Journal Articles
- 2023
[j34]Kerem Akarvardar
, H.-S. Philip Wong:
Technology Prospects for Data-Intensive Computing. Proc. IEEE 111(1): 92-112 (2023)- [j33]Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong:
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE 111(6): 561-574 (2023) - [j32]Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi:
Neural Network Compression for Noisy Storage Devices. ACM Trans. Embed. Comput. Syst. 22(3): 58:1-58:29 (2023) - 2022
- [j31]Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs:
A compute-in-memory chip based on resistive random-access memory. Nat. 608(7923): 504-512 (2022) - [j30]Xin Zheng, Ryan Zarcone, Akash Levy, Win-San Khwa, Priyanka Raina, Bruno A. Olshausen, H.-S. Philip Wong:
High-density analog image storage in an analog-valued non-volatile memory array. Neuromorph. Comput. Eng. 2(4): 44018 (2022) - 2020
- [j29]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin:
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108(4): 478-482 (2020) - [j28]H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri:
Scanning the Issue. Proc. IEEE 108(4): 483-484 (2020) - 2019
- [j27]Mindy D. Bishop, H.-S. Philip Wong, Subhasish Mitra, Max M. Shulaker:
Monolithic 3-D Integration. IEEE Micro 39(6): 16-27 (2019) - [j26]Mohamed M. Sabry Aly, Tony F. Wu, Andrew Bartolo, Yash H. Malviya, William Hwang, Gage Hills, Igor L. Markov, Mary Wootters, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra:
The N3XT Approach to Energy-Efficient Abundant-Data Computing. Proc. IEEE 107(1): 19-48 (2019) - 2018
- [j25]Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Gage Hills, Bryce Hodson, William Hwang, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra:
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration. IEEE J. Solid State Circuits 53(11): 3183-3196 (2018) - 2017
- [j24]Thomas N. Theis, H.-S. Philip Wong:
The End of Moore's Law: A New Beginning for Information Technology. Comput. Sci. Eng. 19(2): 41-50 (2017) - [j23]Haitong Li, Tony F. Wu, Subhasish Mitra, H.-S. Philip Wong:
Resistive RAM-Centric Computing: Design and Modeling Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2263-2273 (2017) - 2016
- [j22]Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra:
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 521-534 (2016) - [j21]Georges G. E. Gielen, Jelle Van Rethy, Jorge Marin, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(5): 577-586 (2016) - 2015
- [j20]Mohamed M. Sabry, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeffrey Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor L. Markov, Kunle Olukotun, Larry T. Pileggi, Eric Pop, Jan M. Rabaey, Christopher Ré, H.-S. Philip Wong, Subhasish Mitra:
Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. Computer 48(12): 24-33 (2015) - [j19]Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra:
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1082-1095 (2015) - 2014
- [j18]Shashikanth Bobba, Jie Zhang, Pierre-Emmanuel Gaillardon, H.-S. Philip Wong, Subhasish Mitra, Giovanni De Micheli:
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits. ACM J. Emerg. Technol. Comput. Syst. 10(4): 33:1-33:19 (2014) - [j17]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hai Wei, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs. IEEE J. Solid State Circuits 49(1): 190-201 (2014) - 2013
- [j16]Jiale Liang, Chih-Wei Stanley Yeh, S. Simon Wong, H.-S. Philip Wong:
Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array. ACM J. Emerg. Technol. Comput. Syst. 9(1): 9:1-9:14 (2013) - [j15]Daesung Lee, W. Scott Lee, Chen Chen, Farzan Fallah, J. Provine, Soogine Chong, John Watkins, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Combinational Logic Design Using Six-Terminal NEM Relays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 653-666 (2013) - [j14]Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong:
Impact of III-V and Ge Devices on Circuit Performance. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1189-1200 (2013) - 2012
- [j13]H.-S. Philip Wong, Heng-Yuan Lee, Shimeng Yu, Yu-Sheng Chen, Yi Wu, Pang-Shiu Chen, Byoungil Lee, Frederick T. Chen, Ming-Jinn Tsai:
Metal-Oxide RRAM. Proc. IEEE 100(6): 1951-1970 (2012) - [j12]Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra:
Carbon Nanotube Robust Digital VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 453-471 (2012) - 2011
- [j11]Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra:
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1103-1113 (2011) - 2010
- [j10]H.-S. Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P. Reifenberg, Bipin Rajendran, Mehdi Asheghi, Kenneth E. Goodson:
Phase Change Memory. Proc. IEEE 98(12): 2201-2227 (2010) - 2008
- [j9]Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong:
Carbon nanotube transistor compact model for circuit design and performance optimization. ACM J. Emerg. Technol. Comput. Syst. 4(2): 7:1-7:20 (2008) - [j8]Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A Multi-Aperture Image Sensor With 0.7 µm Pixels in 0.11 µm CMOS Technology. IEEE J. Solid State Circuits 43(12): 2990-3005 (2008) - [j7]Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra:
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1725-1736 (2008) - 2002
- [j6]H.-S. Philip Wong:
Beyond the conventional transistor. IBM J. Res. Dev. 46(2-3): 133-168 (2002) - 2001
- [j5]David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong:
Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3): 259-288 (2001) - 1999
- [j4]Hon-Sum Philip Wong, David J. Frank, Paul M. Solomon, Clement H. J. Wann, Jefferey J. Welser:
Nanoscale CMOS. Proc. IEEE 87(4): 537-570 (1999) - 1998
- [j3]H.-S. Philip Wong, Albert J. P. Theuwissen:
Digital Imaging. IEEE Micro 18(6): 12-13 (1998) - 1997
- [j2]Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, Hon-Sum Philip Wong:
CMOS scaling into the nanometer regime. Proc. IEEE 85(4): 486-504 (1997) - 1995
- [j1]Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond. IBM J. Res. Dev. 39(1-2): 245-260 (1995)
Conference and Workshop Papers
- 2023
- [c75]H.-L. Chiang, Richard A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Yeong-Her Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, Meng-Hsueh Chiang, K.-H. Kao, B. Pulicherla, J. Cai, C.-S. Chang, K.-W. Su, K.-L. Cheng, T.-J. Yeh, Y.-C. Peng, C. Enz, Mau-Chung Frank Chang, M.-F. Chang, H.-S. Philip Wong, Iuliana P. Radu:
How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. VLSI Technology and Circuits 2023: 1-2 - [c74]F. Huang, B. Saini, L. Wan, H. Lu, X. He, S. Qin, Wilman Tsai, A. Gruverman, Andrew C. Meng, H.-S. Philip Wong, Paul C. McIntyre, S. S. Wong:
First Observation of Ultra-high Polarization (~ 108 μC/cm²) in Nanometer Scaled High Performance Ferroelectric HZO Capacitors with Mo Electrodes. VLSI Technology and Circuits 2023: 1-2 - [c73]Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu:
Building high performance transistors on carbon nanotube channel. VLSI Technology and Circuits 2023: 1-2 - [c72]Kasidit Toprasertpong, Shuhan Liu, Jian Chen, Sumaiya Wahid, Koustav Jana, Wei-Chen Chen, Shengman Li, Eric Pop, H.-S. Philip Wong:
Co-designed Capacitive Coupling-Immune Sensing Scheme for Indium-Tin-Oxide (ITO) 2T Gain Cell Operating at Positive Voltage Below 2 V. VLSI Technology and Circuits 2023: 1-2 - [c71]Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu:
Scaled contact length with low contact resistance in monolayer 2D channel transistors. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c70]Lauren Hoang, Alwin Daus, Sumaiya Wahid, Jimin Kwon, Jung-Soo Ko, Shengjun Qin, Mahnaz Islam, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop:
Bias Stress Stability of ITO Transistors and its Dependence on Dielectric Properties. DRC 2022: 1-2 - [c69]Sumaiya Wahid, Alwin Daus, Jimin Kwon, Shengjun Qin, Jung-Soo Ko, Krishna C. Saraswat, H.-S. Philip Wong, Eric Pop:
First Demonstration of Top-Gated ITO Transistors: Effect of Channel Passivation. DRC 2022: 1-2 - [c68]Wei-Chen Chen, F. Huang, S. Qin, Z. Yu, Q. Lin, Paul C. McIntyre, S. S. Wong, H.-S. Philip Wong:
4 Bits/cell Hybrid 1F1R for High Density Embedded Non-Volatile Memory and its Application for Compute in Memory. VLSI Technology and Circuits 2022: 244-245 - [c67]Ming-Yang Li, Ching-Hao Hsu, Shin-Wei Shen, Ang-Sheng Chou, Yuxuan Cosmi Lin, Chih-Piao Chuu, Ning Yang, Sui-An Chou, Lin-Yun Huang, Chao-Ching Cheng, Wei-Yen Woon, Szuya Liao, Chih-I Wu, Lain-Jong Li, Iuliana P. Radu, H.-S. Philip Wong, Han Wang:
Wafer-Scale Bi-Assisted Semi-Auto Dry Transfer and Fabrication of High-Performance Monolayer CVD WS2 Transistor. VLSI Technology and Circuits 2022: 290-291 - [c66]Asir Intisar Khan, Christopher Perez, Xiangjin Wu, Byoungjun Won, Kangsik Kim, Heungdong Kwon, Pranav Ramesh, Kathryn M. Neilson, Mehdi Asheghi, Krishna Saraswat, Zonghoon Lee, Il-Kwon Oh, H.-S. Philip Wong, Kenneth E. Goodson, Eric Pop:
First Demonstration of Ge2Sb2Te5-Based Superlattice Phase Change Memory with Low Reset Current Density (~3 MA/cm2) and Low Resistance Drift (~0.002 at 105°C). VLSI Technology and Circuits 2022: 310-311 - [c65]Shengjun Qin, Maryann C. Tung, Emma Belliveau, Shuhan Liu, Jimin Kwon, Wei-Chen Chen, Zizhen Jiang, S. Simon Wong, H.-S. Philip Wong:
8-Layer 3D Vertical Ru/AlOxNy/TiN RRAM with Mega-Ω Level LRS for Low Power and Ultrahigh-density Memory. VLSI Technology and Circuits 2022: 314-315 - [c64]S. Vaziri, I. M. Datye, Elia Ambrosi, Asir Intisar Khan, H. Kwon, C. H. Wu, C. F. Hsu, J. Guy, T. Y. Lee, H.-S. Philip Wong, X. Y. Bao:
First Fire-free, Low-voltage (~1.2 V), and Low Off-current (~3 nA) SiOxTey Selectors. VLSI Technology and Circuits 2022: 324-325 - [c63]Sheng-Kai Su, Edward Chen, Terry Y. T. Hung, Meng-Zhan Li, Gregory Pitner, Chao-Ching Cheng, Han Wang, Jin Cai, H.-S. Philip Wong, Iuliana P. Radu:
Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS. VLSI Technology and Circuits 2022: 403-404 - 2020
- [c62]Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs:
A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. ICONS 2020: 18:1-18:4 - [c61]Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong:
33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. ISSCC 2020: 498-500 - 2019
- [c60]Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong:
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. DAC 2019: 131 - [c59]Connor McClellan, Andrew C. Yu, Ching-Hua Wang, H.-S. Philip Wong, Eric Pop:
Vertical Sidewall MoS2 Growth and Transistors. DRC 2019: 65-66 - [c58]H.-S. Philip Wong:
IC Technology - What Will the Next Node Offer Us? Hot Chips Symposium 2019: 1-52 - [c57]Tony F. Wu, Binh Q. Le, Robert M. Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra:
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC 2019: 226-228 - 2018
- [c56]Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra:
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. DAC 2018: 74:1-74:10 - [c55]Ryan Zarcone, Dylan M. Paiton, Alex Anderson, Jesse H. Engel, H.-S. Philip Wong, Bruno A. Olshausen:
Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage. DCC 2018: 147-156 - [c54]Stephanie M. Bohaichuk, Miguel Munoz-Rojo, Gregory Pitner, Connor McClellan, Feifei Lian, Jason Li, Jaewoo Jeong, Mahesh Samant, Stuart Parkin, H.-S. Philip Wong, Eric Pop:
Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters. DRC 2018: 1-2 - [c53]H.-S. Philip Wong:
The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology. DRC 2018: 1-2 - [c52]Eilam Yalon, Kye Okabe, Christopher M. Neumann, H.-S. Philip Wong, Eric Pop:
Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses. DRC 2018: 1-2 - [c51]William Hwang, Weier Wan, Subhasish Mitra, H.-S. Philip Wong:
Coming Up N3XT, After 2D Scaling of Si CMOS. ISCAS 2018: 1-5 - [c50]Tony F. Wu, Haitong Li, Ping-Chen Huang, Abbas Rahimi, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra:
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study. ISSCC 2018: 492-494 - 2017
- [c49]William Hwang, Mohamed M. Sabry Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, Christos Kozyrakis, H.-S. Philip Wong, Subhasish Mitra:
3D nanosystems enable embedded abundant-data computing: special session paper. CODES+ISSS 2017: 29:1-29:2 - [c48]Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Huili Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha:
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. DAC 2017: 17:1-17:6 - [c47]Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC 2017: 18:1-18:2 - 2016
- [c46]Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni:
Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS 2016: 23:1-23:10 - [c45]Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong:
Neuromorphic architectures with electronic synapses. ISQED 2016: 118-123 - [c44]Max Marcel Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Transforming nanodevices to next generation nanosystems. SAMOS 2016: 288-292 - 2015
- [c43]Jinfeng Kang, Haitong Li, Peng Huang, Zhe Chen, Bin Gao, Xiaoyan Liu, Zizhen Jiang, H.-S. Philip Wong:
Modeling and design optimization of ReRAM. ASP-DAC 2015: 576-581 - [c42]Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Contact pitch and location prediction for Directed Self-Assembly template verification. ASP-DAC 2015: 644-651 - [c41]Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong:
Layout optimization and template pattern verification for directed self-assembly (DSA). DAC 2015: 199:1-199:6 - [c40]Max M. Shulaker, Tony F. Wu, Mohamed M. Sabry, Hai Wei, H.-S. Philip Wong, Subhasish Mitra:
Monolithic 3D integration: a path from concept to reality. DATE 2015: 1197-1202 - [c39]Haitong Li, Zizhen Jiang, Peng Huang, Y. Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong:
Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model. DATE 2015: 1425-1430 - [c38]Jinfeng Kang, Bin Gao, Peng Huang, Lifeng Liu, Xiaoyan Liu, H. Y. Yu, Shimeng Yu, H.-S. Philip Wong:
RRAM based synaptic devices for neuromorphic visual systems. DSP 2015: 1219-1222 - [c37]Georges G. E. Gielen, Jelle Van Rethy, Max M. Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra:
Time-based sensor interface circuits in carbon nanotube technology. ISCAS 2015: 2924-2927 - [c36]H.-S. Philip Wong, He Yi, Maryann C. Tung, Kye Okabe:
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning. ISPD 2015: 65-66 - 2014
- [c35]Gage Hills, Max M. Shulaker, Hai Wei, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra:
Robust design and experimental demonstrations of carbon nanotube digital circuits. CICC 2014: 1-4 - [c34]Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Directed Self-Assembly (DSA) Template Pattern Verification. DAC 2014: 55:1-55:6 - [c33]Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan, H.-S. Philip Wong:
Video analytics using beyond CMOS devices. DATE 2014: 1-5 - [c32]Jinfeng Kang, Bin Gao, Bing Chen, Peng Huang, Feifei Zhang, Xiaoyan Liu, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong, Shimeng Yu:
Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture. ISCAS 2014: 417-420 - [c31]Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Zizhen Jiang, H.-S. Philip Wong:
Design guidelines for 3D RRAM cross-point architecture. ISCAS 2014: 421-424 - [c30]Shimeng Yu, Duygu Kuzum, H.-S. Philip Wong:
Design considerations of synaptic device for neuromorphic computing. ISCAS 2014: 1062-1065 - 2013
- [c29]Gage Hills, Jie Zhang, Charles Mackin, Max M. Shulaker, Hai Wei, H.-S. Philip Wong, Subhasish Mitra:
Rapid exploration of processing and design guidelines to overcome carbon nanotube variations. DAC 2013: 105:1-105:10 - [c28]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Sacha: the Stanford carbon nanotube controlled handshaking robot. DAC 2013: 124:1-124:3 - [c27]Hai Wei, Max M. Shulaker, Gage Hills, Hong-Yu Chen, Chi-Shuen Lee, Luckshitha Liyanage, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube circuits: opportunities and challenges. DATE 2013: 619-624 - [c26]Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma:
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. ICCAD 2013: 186-193 - [c25]Max M. Shulaker, Jelle Van Rethy, Gage Hills, Hong-Yu Chen, Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra:
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs. ISSCC 2013: 112-113 - 2012
- [c24]Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing. ASP-DAC 2012: 639 - [c23]Rakesh Gnana David Jeyasingh, Jiale Liang, Marissa Caldwell, Duygu Kuzum, H.-S. Philip Wong:
Phase Change Memory: Scaling and applications. CICC 2012: 1-7 - [c22]Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique. DATE 2012: 1361-1366 - [c21]Xiangyu Chen, Jiale Liang, H.-S. Philip Wong:
Interconnect scaling into the sub-10nm regime. SLIP 2012: 2 - 2011
- [c20]Jason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle:
Circuit-aware device reliability criteria methodology. ESSCIRC 2011: 255-258 - [c19]Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated. ICCAD 2011: 227-230 - 2010
- [c18]Shinobu Fujita, Shinichi Yasuda, Daesung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong:
Detachable nano-carbon chip with ultra low power. DAC 2010: 631-632 - [c17]Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra:
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. DAC 2010: 889-892 - [c16]Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra:
Carbon nanotube circuits: Living with imperfections and variations. DATE 2010: 1159-1164 - [c15]Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Efficient FPGAs using nanoelectromechanical relays. FPGA 2010: 273-282 - [c14]Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. Philip Wong:
Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design. ISQED 2010: 342-346 - [c13]Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H.-S. Philip Wong:
Intel LVS logic as a combinational logic paradigm in CNT technology. NANOARCH 2010: 77-81 - 2009
- [c12]Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra:
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. DAC 2009: 304-309 - [c11]Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong:
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage. ICCAD 2009: 478-484 - [c10]SangBum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, H.-S. Philip Wong:
Fabrication and Characterization of Emerging Nanoscale Memory. ISCAS 2009: 65-68 - 2008
- [c9]Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS. ISSCC 2008: 48-49 - 2007
- [c8]Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra:
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. DAC 2007: 958-961 - [c7]Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong:
Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED 2007: 145-152 - [c6]Jie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong:
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections. ISSCC 2007: 70-588 - 2006
- [c5]Keith Fife, Abbas El Gamal, H.-S. Philip Wong:
A 3D Multi-Aperture Image Sensor Architecture. CICC 2006: 281-284 - [c4]H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan:
Carbon nanotube transistor circuits: models and tools for design and performance optimization. ICCAD 2006: 651-654 - [c3]H.-S. Philip Wong:
Device and Technology Challenges for Nanoscale CMOS. ISQED 2006: 515-518 - 2005
- [c2]H.-S. Philip Wong:
Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts. ESSCIRC 2005: 55-61 - 2002
- [c1]Meikei Leong, H.-S. Philip Wong, Edward J. Nowak, Jakub Kedzierski, Erin C. Jones:
High Performance Double-Gate Device Technology Challenges and Opportunities (invited). ISQED 2002: 492-495
Data and Artifacts
- 2022
- [d1]Asir Intisar Khan, Heungdong Kwon, Raisul Islam, Christopher Perez, Michelle Chen, Mehdi Asheghi, Kenneth E. Goodson, H.-S. Philip Wong, Eric Pop:
Two-Fold Reduction of Switching Current Density in Phase Change Memory Using Bi2Te3 Thermoelectric Interfacial Layer. IEEE DataPort, 2022
Informal and Other Publications
- 2024
- [i15]Keming Fan, Wei-Chen Chen, Sumukh Pinge, H.-S. Philip Wong, Tajana Rosing:
Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory. CoRR abs/2405.02756 (2024) - 2022
- [i14]Richard A. Gottscho, Edlyn V. Levine, Tsu-Jae King Liu, Paul C. McIntyre, Subhasish Mitra, Boris Murmann, Jan M. Rabaey, Sayeef S. Salahuddin, Willy C. Shih, H.-S. Philip Wong:
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies. CoRR abs/2204.02216 (2022) - 2021
- [i13]Berivan Isik, Kristy Choi, Xin Zheng, Tsachy Weissman, Stefano Ermon, H.-S. Philip Wong, Armin Alaghi:
Neural Network Compression for Noisy Storage Devices. CoRR abs/2102.07725 (2021) - [i12]Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs:
Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. CoRR abs/2108.07879 (2021) - [i11]Chi-Shuen Lee, Brian Cline, Saurabh Sinha, Greg Yeric, H.-S. Philip Wong:
Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. CoRR abs/2109.07915 (2021) - 2020
- [i10]Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, H.-S. Philip Wong:
Nanotechnology-inspired Information Processing Systems of the Future. CoRR abs/2005.02434 (2020) - 2018
- [i9]Abbas Rahimi, Tony F. Wu, Haitong Li, Jan M. Rabaey, H.-S. Philip Wong, Max M. Shulaker, Subhasish Mitra:
Hyperdimensional Computing Nanosystem. CoRR abs/1811.09557 (2018) - 2017
- [i8]Jesse H. Engel, Sukru Burc Eryilmaz, SangBum Kim, Matthew BrightSky, Chung Lam, Hsiang-Lan Lung, Bruno A. Olshausen, H.-S. Philip Wong:
Opportunities for Analog Coding in Emerging Memory Systems. CoRR abs/1701.06063 (2017) - 2016
- [i7]Haitong Li, Peng Huang, Bin Gao, Xiaoyan Liu, Jinfeng Kang, H.-S. Philip Wong:
Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays. CoRR abs/1606.07457 (2016) - [i6]Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, SangBum Kim, Matthew BrightSky, Hsiang-Lan Lung, Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong:
Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses. CoRR abs/1609.08686 (2016) - 2015
- [i5]Tony F. Wu, Karthik Ganesan, Yunqing Alexander Hu, H.-S. Philip Wong, S. Simon Wong, Subhasish Mitra:
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. CoRR abs/1505.02211 (2015) - [i4]Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra:
Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. CoRR abs/1507.05679 (2015) - [i3]Sukru Burc Eryilmaz, Duygu Kuzum, Shimeng Yu, H.-S. Philip Wong:
Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures. CoRR abs/1512.08030 (2015) - 2014
- [i2]Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong:
Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices. CoRR abs/1405.7716 (2014) - [i1]Sukru Burc Eryilmaz, Duygu Kuzum, Rakesh Gnana David Jeyasingh, SangBum Kim, Matthew BrightSky, Chung Lam, H.-S. Philip Wong:
Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. CoRR abs/1406.4951 (2014)
Coauthor Index
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