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ORCIDMichele Favalli
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Journal Articles
- 2016
[j39]Michele Favalli, Marcello Dalpasso
:
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults. IEEE Trans. Computers 65(3): 706-715 (2016)- 2014
- [j38]Michele Favalli, Marcello Dalpasso:
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits. J. Electron. Test. 30(1): 41-55 (2014) - [j37]L. Valenti, Marcello Dalpasso, Michele Favalli:
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits. IET Comput. Digit. Tech. 8(2): 83-89 (2014) - 2013
- [j36]Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi:
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12(4): 106:1-106:29 (2013) - 2011
- [j35]Santino Mele, Michele Favalli:
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 631-635 (2011) - 2009
- [j34]Michele Favalli, Marcello Dalpasso:
How Many Test Vectors We Need to Detect a Bridging Fault? J. Electron. Test. 25(1): 79-95 (2009) - [j33]Michele Favalli, Cecilia Metra:
Testing Resistive Opens and Bridging Faults Through Pulse Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 915-925 (2009) - 2006
- [j32]Michele Favalli:
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems. IEEE Trans. Computers 55(3): 348-352 (2006) - 2005
- [j31]Michele Favalli:
A fuzzy model for path delay fault detection. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 943-956 (2005) - 2004
- [j30]Michele Favalli, Cecilia Metra:
TMR voting in the presence of crosstalk faults at the voter inputs. IEEE Trans. Reliab. 53(3): 342-348 (2004) - 2003
- [j29]Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò:
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. Microelectron. J. 34(1): 23-29 (2003) - [j28]Cecilia Metra, Luca Schiano, Michele Favalli:
Concurrent detection of power supply noise. IEEE Trans. Reliab. 52(4): 469-475 (2003) - 2002
- [j27]Michele Favalli, Cecilia Metra:
Online Testing Approach for Very Deep-Submicron ICs. IEEE Des. Test Comput. 19(2): 16-23 (2002) - [j26]Michele Favalli, Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. J. Electron. Test. 18(3): 273-283 (2002) - [j25]Cecilia Metra, Michele Favalli, Stefano Di Francescantonio, Bruno Riccò:
On-Chip Clock Faults' Detector. J. Electron. Test. 18(4-5): 555-564 (2002) - [j24]Michele Favalli, Marcello Dalpasso:
Bridging fault modeling and simulation for deep submicron CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 941-953 (2002) - 2000
- [j23]Michele Favalli, Cecilia Metra:
Bridging Faults in Pipelined Circuits. J. Electron. Test. 16(6): 617-629 (2000) - [j22]Cecilia Metra, Michele Favalli, Bruno Riccò:
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines. IEEE Trans. Computers 49(6): 560-574 (2000) - [j21]Alessandro Bogliolo, Michele Favalli, Maurizio Damiani:
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 415-419 (2000) - [j20]Cecilia Metra, Michele Favalli, Bruno Riccò:
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits. VLSI Design 11(1): 23-34 (2000) - 1999
- [j19]Michele Favalli, Cecilia Metra:
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 392-396 (1999) - 1998
- [j18]Cecilia Metra, Michele Favalli, Bruno Riccò:
Concurrent Checking of Clock Signal Correctness. IEEE Des. Test Comput. 15(4): 42-48 (1998) - [j17]Luca Benini, Alessandro Bogliolo, Michele Favalli, Giovanni De Micheli:
Regression Models for Behavioral Power Estimation. Integr. Comput. Aided Eng. 5(2): 95-106 (1998) - 1997
- [j16]Michele Favalli, Marcello Dalpasso:
Symbolic Handling of Bridging Fault Effects. J. Electron. Test. 10(3): 271-276 (1997) - [j15]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 770-776 (1997) - [j14]Marcello Dalpasso, Michele Favalli:
A method for increasing the IDDQ testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1186-1188 (1997) - 1996
- [j13]Michele Favalli, Marcello Dalpasso, Piero Olivo:
Modeling and simulation of broken connections in CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 808-814 (1996) - [j12]Michele Favalli, Cecilia Metra:
Sensing circuit for on-line detection of delay faults. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 130-133 (1996) - 1995
- [j11]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults. J. Electron. Test. 6(1): 7-22 (1995) - 1993
- [j10]Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò:
Fault simulation of parametric bridging faults in CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1403-1410 (1993) - [j9]Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analysis of resistive bridging fault detection in BiCMOS digital ICs. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 342-355 (1993) - 1992
- [j8]Michele Favalli, Piero Olivo, Bruno Riccò:
Dynamic effects in the detection of bridging faults in CMOS ICs. J. Electron. Test. 3(3): 197-205 (1992) - [j7]Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò:
Testability measures in pseudorandom testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 794-800 (1992) - [j6]Michele Favalli, Piero Olivo, Bruno Riccò:
A probabilistic fault model for 'analog' faults in digital CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1459-1462 (1992) - 1991
- [j5]Michele Favalli, Piero Olivo, Bruno Riccò, Fabio Somenzi:
Fault simulation for general FCMOS ICs. J. Electron. Test. 2(2): 181-190 (1991) - [j4]Michele Favalli, Piero Olivo, Bruno Riccò:
A novel critical path heuristic for fast fault grading. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 544-548 (1991) - [j3]Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò:
Fault simulation of unconventional faults in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(5): 677-682 (1991) - 1990
- [j2]Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, Bruno Riccò:
Aliasing in signature analysis testing with multiple input shift registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1344-1353 (1990) - 1989
- [j1]Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò:
An analytical model for the aliasing probability in signature analysis testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(11): 1133-1144 (1989)
Conference and Workshop Papers
- 2024
- [c53]Alessandro Veronesi, Alessandro Nazzari, Dario Passarello, Milos Krstic, Michele Favalli, Luca Cassano, Antonio Miele, Davide Bertozzi, Cristiana Bolchini:
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space. ETS 2024: 1-6 - 2023
- [c52]Elena Bellodi, Davide Bertozzi, Alice Bizzarri, Michele Favalli, Michele Fraccaroli, Riccardo Zese:
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach. MCSoC 2023: 171-178 - 2022
- [c51]Alessandro Veronesi, Francesco Dall'Occo, Davide Bertozzi, Michele Favalli, Milos Krstic:
Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study. DDECS 2022: 142-147 - 2021
- [c50]Francesco Dall'Occo, Andrés Bueno-Crespo, José L. Abellán, Davide Bertozzi, Michele Favalli:
The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks. SAMOS 2021: 505-522 - 2018
- [c49]Marcello Dalpasso, Davide Bertozzi, Michele Favalli:
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices. DATE 2018: 297-300 - 2016
- [c48]Gabriele Miorandi, Alberto Celin, Michele Favalli, Davide Bertozzi:
A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations. NOCS 2016: 1-8 - 2012
- [c47]Alberto Ghiribaldi, Alessandro Strano, Michele Favalli, Davide Bertozzi:
Power efficiency of switch architecture extensions for fault tolerant NoC design. IGCC 2012: 1-6 - 2011
- [c46]Alessandro Strano, Crispín Gómez Requena, Daniele Ludovici, Michele Favalli, María Engracia Gómez, Davide Bertozzi:
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture. DATE 2011: 661-666 - [c45]Alberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi:
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic. VLSI-SoC 2011: 308-313 - 2007
- [c44]Michele Favalli, Cecilia Metra:
Interactive presentation: Pulse propagation for the detection of small delay defects. DATE 2007: 1295-1300 - [c43]Michele Favalli:
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth. DFT 2007: 170-178 - [c42]Michele Favalli, Marcello Dalpasso:
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations. DFT 2007: 448-456 - 2004
- [c41]Michele Favalli:
"Victim Gate" Crosstalk Fault Model. DFT 2004: 191-199 - [c40]Michele Favalli:
Annotated Bit Flip Fault Model. DFT 2004: 366-376 - 2002
- [c39]Michele Favalli, Cecilia Metra:
Problems Due to Open Faults in the Interconnections of Self-Checking Data-Paths. DATE 2002: 612-617 - [c38]Cecilia Metra, Luca Schiano, Bruno Riccò, Michele Favalli:
Self-Checking Scheme for the On-Line Testing of Power Supply Noise. DATE 2002: 832-836 - [c37]Michele Favalli, Marcello Dalpasso:
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators. DATE 2002: 1122 - 2001
- [c36]Michele Favalli, Cecilia Metra:
Optimization of error detecting codes for the detection of crosstalk originated errors. DATE 2001: 290-296 - [c35]Michele Favalli, Cecilia Metra:
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. IOLTW 2001: 100-105 - 2000
- [c34]Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli:
Virtual Fault Simulation of Distributed IP-Based Designs. DATE 2000: 99-103 - [c33]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. DATE 2000: 763 - 1999
- [c32]Michele Favalli, Cecilia Metra:
On the Design of Self-Checking Functional Units Based on Shannon Circuits. DATE 1999: 368-375 - 1998
- [c31]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n Code Checker with Single Output. DATE 1998: 981-982 - [c30]Cecilia Metra, Michele Favalli, Bruno Riccò:
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks. DFT 1998: 174-182 - [c29]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-line detection of logic errors due to crosstalk, delay, and transient faults. ITC 1998: 524-533 - 1997
- [c28]Michele Favalli, Cecilia Metra:
Testing scheme for IC's clocks. ED&TC 1997: 445-449 - [c27]Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and low power on-line self-testing voting scheme. DFT 1997: 137-147 - [c26]Michele Favalli, Cecilia Metra:
Low-level error recovery mechanism for self-checking sequential circuits. DFT 1997: 234-242 - [c25]Cecilia Metra, Michele Favalli, Bruno Riccò:
On-Line Testing Scheme for Clock's Faults. ITC 1997: 587-596 - [c24]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly testable and compact single output comparator. VTS 1997: 210-215 - 1996
- [c23]Michele Favalli, Luca Benini, Giovanni De Micheli:
Design for Testability of Gated-Clock FSMs. ED&TC 1996: 589-597 - [c22]Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and Highly Testable Error Indicator for Self-Checking Circuits. DFT 1996: 204-212 - [c21]Cecilia Metra, Michele Favalli, Bruno Riccò:
Tree Checkers for Applications with Low Power-Delay Requirements. DFT 1996: 213-220 - [c20]Cecilia Metra, Michele Favalli, Bruno Riccò:
Embedded two-rail checkers with on-line testing ability. VTS 1996: 145-150 - 1995
- [c19]Marcello Dalpasso, Michele Favalli, Piero Olivo:
Correlation between IDDQ testing quality and sensor accuracy. ED&TC 1995: 568-572 - [c18]Michele Favalli, Bruno Riccò, L. Penza:
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs. ED&TC 1995: 599 - [c17]Cecilia Metra, Michele Favalli, Bruno Riccò:
Novel Berger code checker. DFT 1995: 287-295 - [c16]Michele Favalli, Luca Benini:
Analysis of glitch power dissipation in CMOS ICs. ISLPD 1995: 123-128 - [c15]Marcello Dalpasso, Michele Favalli, Piero Olivo:
Test pattern generation for IDDQ: increasing test quality. VTS 1995: 304-309 - 1994
- [c14]Cecilia Metra, Michele Favalli, Bruno Riccò:
CMOS Self Checking Circuits with Faulty Sequential Functional Block. DFT 1994: 133-141 - [c13]Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n CMOS Checkers. DFT 1994: 142-150 - [c12]Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Modeling of Broken Connections Faults in CMOS ICs. EDAC-ETC-EUROASIC 1994: 159-164 - 1993
- [c11]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. DFT 1993: 271-278 - [c10]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
A Highly Testable 1-out-of-3 CMOS Checker. DFT 1993: 279-286 - [c9]Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs. ITC 1993: 865-874 - 1992
- [c8]Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs. ITC 1992: 466-475 - [c7]Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò:
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs. ITC 1992: 486-495 - [c6]Cecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò:
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults. ITC 1992: 948-957 - 1991
- [c5]M. Ambanelli, Michele Favalli, Piero Olivo, Bruno Riccò:
Detection of PLA multiple crosspoint faults. EURO-DAC 1991: 80-84 - [c4]Michele Favalli, Piero Olivo, Bruno Riccò:
A probabilistic fault model for analog faults. EURO-DAC 1991: 85-88 - 1989
- [c3]Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò:
Improved testability evaluations in combinational logic networks. ICCD 1989: 352-355 - [c2]Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò:
CMOS Design for Improved IC Testability. ITC 1989: 934 - 1988
- [c1]Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò:
Aliasing errors in signature analysis testing of integrated circuits. ICCD 1988: 458-461
Coauthor Index
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