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Witold A. Pleskacz
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Journal Articles
- 2020
- [j10]Krzysztof Marcinek
, Witold A. Pleskacz
:
GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing. Sensors 20(2): 465 (2020) - [j9]Tomasz Borejko, Krzysztof Marcinek
, Krzysztof Siwiec
, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
:
NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 20(4): 1069 (2020) - [j8]Tomasz Borejko, Krzysztof Marcinek
, Krzysztof Siwiec, Pawel Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz W. Luczyk, Daniel Pietron, Maciej Plasota, Szymon Reszewicz, Lukasz Wiechowski, Witold A. Pleskacz
:
Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069. Sensors 20(19): 5544 (2020) - 2018
- [j7]Zoran Stamenkovic, Ondrej Novák, Witold A. Pleskacz:
Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017). Microelectron. Reliab. 81: 287 (2018) - 2013
- [j6]Krzysztof Marcinek
, Witold A. Pleskacz:
ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model. Microprocess. Microsystems 37(6-7): 693-700 (2013) - 2008
- [j5]Witold A. Pleskacz, Viera Stopjaková
, Tomasz Borejko, Artur Jutman
, Andrzej Walkanis:
DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits. IEEE Trans. Ind. Electron. 55(6): 2405-2415 (2008) - 2003
- [j4]Dominik Kasprowicz
, Witold A. Pleskacz:
Improvement of integrated circuit testing reliability by using the defect based approach. Microelectron. Reliab. 43(6): 945-953 (2003) - 2002
- [j3]T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz
, Witold A. Pleskacz, Jaan Raik
, Raimund Ubar:
Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. 42(7): 1141-1149 (2002) - 2001
- [j2]Mykola Blyzniuk, Irena Kazymyra
, Wieslaw Kuzmicz
, Witold A. Pleskacz, Jaan Raik
, Raimund Ubar:
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. 41(12): 2023-2040 (2001) - 1999
- [j1]Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly:
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 151-162 (1999)
Conference and Workshop Papers
- 2024
- [c75]Marika Grochowska, Witold A. Pleskacz:
The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. DDECS 2024: 37-40 - [c74]Bohdan Shveida, Krzysztof Marcinek, Witold A. Pleskacz:
Implementation of Hardware Trace Buffer Module for RISC-V Processor Core. MIXDES 2024: 110-113 - [c73]Jakub Misztal, Mateusz Korona, Witold A. Pleskacz:
Bridge Circuit Converting Atomic Transactions Between AMBA AXI4 and AMBA AXI5 Standards. MIXDES 2024: 249-253 - 2023
- [c72]Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz:
Dual TDL Based Phase Difference Detector Architecture. MIXDES 2023: 122-126 - 2022
- [c71]Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz:
Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits. MIXDES 2022: 89-92 - [c70]Adam Borkowski, Krzysztof Siwiec, Witold A. Pleskacz:
DC/DC Buck Converter Soft-Start Methods. MIXDES 2022: 131-135 - 2021
- [c69]Pawel Pienczuk, Witold A. Pleskacz, Mateusz Teodorowski:
Class AB Operational Amplifier in CMOS 55 nm Technology. MIXDES 2021: 90-93 - 2020
- [c68]Szymon Reszewicz, Krzysztof Siwiec
, Witold A. Pleskacz:
CMOS Differential Amplifier as a Physically Unclonable Function. DDECS 2020: 1-4 - 2019
- [c67]Mariusz Derlecki, Krzysztof Siwiec
, Pawel Narczyk, Witold A. Pleskacz:
Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter. DDECS 2019: 1-4 - [c66]Zoran Stamenkovic
, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger
, Goran Stojanovic
, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - [c65]Adam Borkowski, Tomasz Borejko, Witold A. Pleskacz:
DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology. MIXDES 2019: 196-199 - [c64]Adrian Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Witold A. Pleskacz:
Design and Verification Environment for RISC-V Processor Cores. MIXDES 2019: 206-209 - [c63]Lukasz Ostrowski, Krzysztof Marcinek, Witold A. Pleskacz:
Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication. MIXDES 2019: 227-230 - [c62]Sebastian Cieslak, Adrian Oleksiak, Krzysztof Marcinek, Witold A. Pleskacz:
Retargeting the MIPS-II CPU Core to the RISC-V Architecture. MIXDES 2019: 261-264 - [c61]Andrzej A. Wojciechowski, Krzysztof Marcinek, Witold A. Pleskacz:
Configurable MBIST Processor for Embedded Memories Testing. MIXDES 2019: 341-344 - 2018
- [c60]Szymon Reszewicz, Krzysztof Siwiec
, Witold A. Pleskacz:
2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. DDECS 2018: 113-116 - [c59]Daniel Pietron, Igor Butryn, Lukasz Wiechowski, Witold A. Pleskacz:
Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology. MIXDES 2018: 131-135 - [c58]Igor Butryn, Lukasz Wiechowski, Daniel Pietron, Witold A. Pleskacz:
Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology. MIXDES 2018: 160-164 - 2017
- [c57]Pawel Narczyk, Krzysztof Siwiec
, Witold A. Pleskacz:
Analog front-end for precise human body temperature measurement. DDECS 2017: 67-72 - [c56]Michal Wysocki, Krzysztof Siwiec
, Witold A. Pleskacz:
EIA/TIA-485 transceiver in standard 130 nm CMOS technology. MIXDES 2017: 258-263 - [c55]Pawel Narczyk, Krzysztof Siwiec
, Witold A. Pleskacz:
Temperature calibration technique based on on-chip resistor. MIXDES 2017: 328-332 - [c54]Daniel Pietron, Tomasz Borejko, Krzysztof Siwiec
, Witold A. Pleskacz:
Importance of on-chip inductor modeling in radio frequency integrated circuits. MIXDES 2017: 398-403 - [c53]Arkadiusz W. Luczyk, Konrad Neneman, Witold A. Pleskacz:
Principal component analysis of accelerations in human dynamic movements: A sample set length effect study. MIXDES 2017: 601-606 - 2016
- [c52]Krzysztof Siwiec
, Krzysztof Marcinek
, Piotr Boguszewicz, Tomasz Borejko, Aleh Halauko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus
, Witold A. Pleskacz:
BioSoC: Highly integrated System-on-Chip for health monitoring. DDECS 2016: 102-107 - [c51]Pawel Narczyk, Krzysztof Siwiec
, Witold A. Pleskacz:
Precision human body temperature measurement based on thermistor sensor. DDECS 2016: 108-112 - [c50]Igor Butryn, Krzysztof Siwiec
, Jakub Kopanski, Witold A. Pleskacz:
Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology. DDECS 2016: 218-221 - [c49]Cezary Kolacinski
, Jerzy Wasowski, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Tomasz Borejko, Krzysztof Siwiec
, Witold A. Pleskacz:
Dedicated chip for pulse oximetry measurements. EWDTS 2016: 1-4 - [c48]Marek Cieplucha, Witold A. Pleskacz:
New architecture of the object-oriented functional coverage mechanism for digital verification. IVSW 2016: 1-6 - [c47]Jakub Kopanski, Lukasz Wiechowski, Krzysztof Siwiec
, Witold A. Pleskacz:
A low sampling frequency switched capacitor low-pass filter for wireless receivers. MIXDES 2016: 130-135 - [c46]Pawel Wiecha, Marek Cieplucha, Patryk Kloczko, Witold A. Pleskacz:
Architecture and design of a Bluetooth Low Energy Controller. MIXDES 2016: 164-167 - [c45]Cezary Kolacinski
, Andrzej Szymanski, Adam Jarosz, Ewa Kurjata-Pfitzner, Jerzy Wasowski, Tomasz Borejko, Krzysztof Siwiec
, Witold A. Pleskacz:
The integrated transmitter and receiver modules for pulse oximeter system. MIXDES 2016: 243-248 - [c44]Konrad Neneman, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Monitoring of dynamic movements using acceleration measurements. MIXDES 2016: 515-518 - 2015
- [c43]Andrzej Grodzicki, Witold A. Pleskacz:
A Low Ripple Current Mode Voltage Doubler. DDECS 2015: 63-68 - [c42]Maciej Moskala, Patryk Kloczko, Marek Cieplucha, Witold A. Pleskacz:
UVM-based Verification of Bluetooth Low Energy Controller. DDECS 2015: 123-124 - [c41]Krzysztof Marcinek
, Maciej Plasota, Andrzej Wielgus
, Witold A. Pleskacz:
Implementation of the ADELITE Microcontroller for Biomedical Applications. DDECS 2015: 271-274 - [c40]Krzysztof Siwiec
, Krzysztof Marcinek
, Tomasz Borejko, Adam Jarosz, Jakub Kopanski, Ewa Kurjata-Pfitzner, Pawel Narczyk, Maciej Plasota, Andrzej Wielgus
, Witold A. Pleskacz:
A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring. MIXDES 2015: 37-42 - [c39]Mariusz Derlecki, Tomasz Borejko, Witold A. Pleskacz:
IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology. MIXDES 2015: 334-338 - [c38]Aleh Halauko, Tomasz Borejko, Witold A. Pleskacz:
Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications. MIXDES 2015: 354-358 - 2014
- [c37]Andrzej Grodzicki, Witold A. Pleskacz:
Multistage low ripple charge pump. DDECS 2014: 93-98 - [c36]Daniel Pietron, Krzysztof Siwiec
, Jakub Kopanski, Witold A. Pleskacz:
Implementation of the Bluetooth receiver RF front-end in the CMOS-RF 130 nm technology. MIXDES 2014: 230-235 - [c35]Lukasz Wiechowski, Krzysztof Siwiec
, Jakub Kopanski, Witold A. Pleskacz:
Simulink model of GFSK demodulator based on time-to-digital converter. MIXDES 2014: 338-341 - 2013
- [c34]Krzysztof Siwiec
, Aleksander Koter, Witold A. Pleskacz:
Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies. DDECS 2013: 165-169 - 2012
- [c33]Krzysztof Marcinek
, Witold A. Pleskacz:
AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems. DDECS 2012: 26-29 - [c32]Krzysztof Siwiec
, Tomasz Borejko, Witold A. Pleskacz:
LC-VCO design automation tool for nanometer CMOS technology. DDECS 2012: 68-73 - 2011
- [c31]Krzysztof Siwiec
, Tomasz Borejko, Witold A. Pleskacz:
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications. DDECS 2011: 29-34 - [c30]Michal Lukaszewicz, Tomasz Borejko, Witold A. Pleskacz:
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations. DDECS 2011: 75-79 - [c29]Jakub Kopanski, Witold A. Pleskacz, Dariusz Pienkowski:
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology. DDECS 2011: 131-134 - [c28]Krzysztof Siwiec
, Tomasz Borejko, Witold A. Pleskacz:
CAD tool for PLL Design. DDECS 2011: 283-286 - 2010
- [c27]Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz:
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies. DDECS 2010: 213-216 - 2009
- [c26]Jacek Gradzki, Tomasz Borejko, Witold A. Pleskacz:
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. DDECS 2009: 78-83 - [c25]Peter Malík, Michal Ufnal, Arkadiusz W. Luczyk, Marcel Baláz, Witold A. Pleskacz:
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. DDECS 2009: 144-147 - [c24]Krzysztof Marcinek
, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Enhanced LEON3 core for superscalar processing. DDECS 2009: 238-241 - 2008
- [c23]Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. DDECS 2008: 14-17 - [c22]Tomasz Borejko, Witold A. Pleskacz:
A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. DDECS 2008: 38-43 - [c21]Peter Malík, Marcel Baláz, Martin Simlastík, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Various MDCT implementations in 0.35µm CMOS. DDECS 2008: 170-173 - [c20]Marcin J. Beresinski, Tomasz Borejko, Witold A. Pleskacz, Viera Stopjaková
:
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. DDECS 2008: 259-262 - [c19]Witold A. Pleskacz, Maksim Jenihhin
, Jaan Raik
, Michal Rakowski, Raimund Ubar
, Wieslaw Kuzmicz
:
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD 2008: 729-734 - [c18]Andrzej Wielgus
, Witold A. Pleskacz:
Characterization of CMOS sequential standard cells for defect based voltage testing. EWDTS 2008: 49-54 - 2007
- [c17]Maksim Jenihhin
, Jaan Raik
, Raimund Ubar
, Witold A. Pleskacz, Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40 - [c16]Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz:
Power Dissipation in Basic Global Clock Distribution Networks. DDECS 2007: 231-234 - [c15]Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz:
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. DDECS 2007: 423-428 - 2006
- [c14]Witold A. Pleskacz, Tomasz Borejko, Andrzej Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar:
DefSim: CMOS Defects on Chip for Research and Education. LATW 2006: 74-79 - 2005
- [c13]Joachim Sudbrock, Jaan Raik
, Raimund Ubar
, Wieslaw Kuzmicz
, Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82 - [c12]Jaan Raik
, Raimund Ubar
, Joachim Sudbrock, Wieslaw Kuzmicz
, Witold A. Pleskacz:
DOT: new deterministic defect-oriented ATPG tool. ETS 2005: 96-101 - 2002
- [c11]Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
:
CMOS Standard Cells Characterization for IDDQ Testing. DFT 2002: 390-398 - 2001
- [c10]Witold A. Pleskacz, Dominik Kasprowicz
, Tomasz Oleszczak, Wieslaw Kuzmicz
:
CMOS Standard Cells Characterization for Defect Based Testing. DFT 2001: 384- - [c9]Wieslaw Kuzmicz
, Witold A. Pleskacz, Jaan Raik
, Raimund Ubar:
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371 - 2000
- [c8]Mykola Blyzniuk, Taras Panchak, Wieslaw Kuzmicz
, Witold A. Pleskacz:
Graphical user interface of FIESTA - software for faults identification and estimation of testability of VLSI circuits. CCU 2000: 127-136 - [c7]Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz
, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Hierarchical defect-oriented fault simulation for digital circuits. ETW 2000: 69-74 - 1999
- [c6]Witold A. Pleskacz:
Yield Estimation of VLSI Circuits with Downscaled Layouts. DFT 1999: 55-60 - 1997
- [c5]Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface. DAC 1997: 321-326 - [c4]Witold A. Pleskacz, Wojciech Maly:
Improved Yield Model for Submicron Domain. DFT 1997: 2-10 - [c3]Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken:
Detection of Yield Trends. DFT 1997: 62-68 - 1996
- [c2]Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly:
Extraction of critical areas for opens in large VLSI circuits. DFT 1996: 21-29 - 1995
- [c1]Witold A. Pleskacz, Wieslaw Kuzmicz:
SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. ED&TC 1995: 598
Editorship
- 2015
- [e2]Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus:
18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-6779-7 [contents] - 2012
- [e1]Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin:
IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012. IEEE 2012, ISBN 978-1-4673-1187-8 [contents]
Coauthor Index
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