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"Yield Estimation of VLSI Circuits with Downscaled Layouts."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Witold A. Pleskacz (1999)

Trier

Dagstuhl

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DOI: 10.1109/DFTVS.1999.802869

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Witold A. Pleskacz:
Yield Estimation of VLSI Circuits with Downscaled Layouts. DFT 1999: 55-60

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last updated on 2023-03-24 00:02 CET by the dblp team

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