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ORCIDDimitrios Velenis
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2020 – today
- 2024
[c32]Qingzhong Deng, Ahmed H. El-Saeed, Alaa Elshazly, Guy Lepage, Chiara Marchese, Hakim Kobbi, Rafal Magdziak, Jeroen De Coster, Neha Singh, Marko Ersek Filipcic, Kristof Croes, Dimitrios Velenis, Maumita Chakrabarti, Peter De Heyn, Peter Verheyen, Philippe Absil, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout:
32×100 GHz WDM filter based on ultra-compact silicon rings with a high thermal tuning efficiency of 5.85 mW/π. OFC 2024: 1-3- [c31]Pengfei Xu, Junwen He, Koen Kennes, Anton Dvoretskii, Arnita Podpod, Guy Lepage, Negin Golshani, Rafal Magdziak, Swetanshu Bipul, Dieter Bode, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Yoojin Ban, Filippo Ferraro, Joris Van Campenhout:
Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer. OFC 2024: 1-3 - [c30]Pengfei Xu, Chiara Marchese, Guy Lepage, Negin Golshani, Ruben Van Eenaeme, Andrea Mingardi, Joost Van Ongeval, Rafal Magdziak, Luc Halipre, Darko Trivkovic, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout:
Low-loss, multi-reticle stitched SiN waveguides for 300mm wafer-level optical interconnects. OFC 2024: 1-3 - 2023
- [c29]Yoojin Ban, Minkyu Kim, Peter De Heyn, Davide Guermandi, Filippo Ferraro, Natarajan Rajasekaran, Peter Verheyen, Pieter Bex, Junwen He, Hakim Kobbi, Jeroen De Coster, Rafal Magdziak, Dieter Bode, Sebastien Lardenois, Nicolas Pantano, Dimitrios Velenis, Joris Van Campenhout:
Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers. OFC 2023: 1-3 - 2022
- [j7]Hesheng Lin
, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne:
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 661-665 (2022) - [j6]Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne:
Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1748-1756 (2022) - [c28]Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke:
(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits 2022: 256-257 - 2021
- [c27]Kenichi Miyaguchi, Yoojin Ban, Nicolas Pantano, Xiao Sun, Philippe Absil, Lieve Bogaerts, Peter Verheyen, Dimitrios Velenis, Marianna Pantouvaki, Joris Van Campenhout:
110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules. ECOC 2021: 1-4
2010 – 2019
- 2019
- [j5]Ioannis A. Papistas, Vasilis F. Pavlidis, Dimitrios Velenis:
Fabrication Cost Analysis for Contactless 3-D ICs. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 758-762 (2019) - [c26]Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne:
Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC 2019: 1-6 - [c25]Yefan Liu, Hao Yu, Gaspard Hiblot, Anastasiia Kruv, Marc Schaekers, Naoto Horiguchi, Dimitrios Velenis, Ingrid De Wolf:
Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. IRPS 2019: 1-5 - 2015
- [c24]Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne:
Processing active devices on Si interposer and impact on cost. 3DIC 2015: TS11.2.1-TS11.2.4 - [c23]Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean:
Active-lite interposer for 2.5 & 3D integration. VLSIC 2015: 222- - 2013
- [c22]Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne:
Si interposer build-up options and impact on 3D system cost. 3DIC 2013: 1-5 - 2012
- [j4]Michele Stucchi, Dimitrios Velenis, Guruprasad Katti:
Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. IEEE Trans. Instrum. Meas. 61(7): 1979-1990 (2012) - 2011
- [j3]Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal:
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits 46(1): 293-307 (2011) - [c21]Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne:
3D stacking using ultra thin dies. 3DIC 2011: 1-5 - [c20]Karen Qian, Karl Malachowski, Paolo Fiorini, Dimitrios Velenis, Maaike Op de Beeck, Chris Van Hoof:
Development of cost-effective biocompatible packaging for microelectronic devices. EMBC 2011: 7674-7677 - 2010
- [c19]Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne:
Cost effectiveness of 3D integration options. 3DIC 2010: 1-6 - [c18]Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis:
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. ETS 2010: 36-41 - [c17]Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal:
3D integration: Circuit design, test, and reliability challenges. IOLTS 2010: 217 - [c16]Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne:
Design issues and considerations for low-cost 3D TSV IC technology. ISSCC 2010: 148-149
2000 – 2009
- 2009
- [j2]William R. Roberts, Dimitrios Velenis:
Effects of Parameter Variations on Timing Characteristics of Clocked Registers. J. Circuits Syst. Comput. 18(7): 1309-1320 (2009) - [c15]Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne:
Impact of 3D design choices on manufacturing cost. 3DIC 2009: 1-5 - 2007
- [c14]Boyan Semerdjiev, Dimitrios Velenis:
Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. ISCAS 2007: 1125-1128 - [c13]Boyan Semerdjiev, Dimitrios Velenis:
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. VLSI Design 2007: 289-294 - 2006
- [c12]William R. Roberts, Dimitrios Velenis:
Effects of process and environmental variations on timing characteristics of clocked registers. ACM Great Lakes Symposium on VLSI 2006: 165-168 - [c11]Itisha Chanodia, Dimitrios Velenis:
Effects of crosstalk noise on H-tree clock distribution networks. ISCAS 2006 - [c10]William R. Roberts, Dimitrios Velenis:
Power supply variation effects on timing characteristics of clocked registers. ISCAS 2006 - [c9]Itisha Chanodia, Dimitrios Velenis:
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. ISVLSI 2006: 456-457 - 2005
- [c8]William R. Roberts, Dimitrios Velenis:
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. PATMOS 2005: 508-517 - 2004
- [c7]Dimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman:
Buffer sizing for delay uncertainty induced by process variations. ICECS 2004: 415-418 - [c6]Dimitrios Velenis, Eby G. Friedman:
Buffer Sizing for Crosstalk Induced Delay Uncertainty. PATMOS 2004: 750-759 - [c5]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Clock tree layout design for reduced delay uncertainty. SoCC 2004: 179-180 - 2003
- [c4]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075 - 2002
- [j1]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. 11(3): 231-246 (2002) - [c3]Dimitrios Velenis, Dimitrios Kalogeras, Basil S. Maglaris:
SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links. NETWORKING 2002: 1233-1238 - 2001
- [c2]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. ICECS 2001: 1021-1025 - [c1]Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425
Coauthor Index
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