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ORCIDJie-Hong Roland Jiang
Jie-Hong R. Jiang
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- affiliation: National Taiwan University, Taipei, Taiwan
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2020 – today
- 2024
[c112]Yu-Wei Fan
, Jie-Hong R. Jiang:
Unifying Decision and Function Queries in Stochastic Boolean Satisfiability. AAAI 2024: 7995-8003- [c111]Che Cheng, Yun-Rong Luo, Jie-Hong R. Jiang:
Knowledge Compilation for Incremental and Checkable Stochastic Boolean Satisfiability. IJCAI 2024: 1862-1872 - [c110]Wei-Hsiang Tseng, Yao-Wen Chang, Jie-Hong Roland Jiang:
Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. ISPD 2024: 245-253 - [e1]Supratik Chakraborty, Jie-Hong Roland Jiang:
27th International Conference on Theory and Applications of Satisfiability Testing, SAT 2024, August 21-24, 2024, Pune, India. LIPIcs 305, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2024, ISBN 978-3-95977-334-8 [contents] - 2023
- [j28]Yun-Rong Luo, Che Cheng, Jie-Hong R. Jiang:
A Resolution Proof System for Dependency Stochastic Boolean Satisfiability. J. Autom. Reason. 67(3): 26 (2023) - [j27]Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko:
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 473-482 (2023) - [j26]Yu-Shan Huang, Jie-Hong R. Jiang:
Circuit Learning: From Decision Trees to Decision Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3985-3996 (2023) - [c109]Che Cheng, Jie-Hong R. Jiang:
Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT. AAAI 2023: 3906-3914 - [c108]Yu-Wei Fan, Jie-Hong R. Jiang:
SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver. AAAI 2023: 3949-3958 - [c107]Jie-Hong R. Jiang:
Second-Order Quantified Boolean Logic. AAAI 2023: 4007-4015 - [c106]Chun-Yu Wei, Jie-Hong R. Jiang:
Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration. DAC 2023: 1-6 - [c105]Kuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan, Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang:
WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits. ICCAD 2023: 1-9 - [c104]Tian-Fu Chen, Chun-Yu Wei, Jie-Hong R. Jiang:
VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion. QCE 2023: 1033-1043 - 2022
- [j25]Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken:
Design and Automation for Quantum Computation and Quantum Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 581-583 (2022) - [j24]Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken:
Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 584-601 (2022) - [j23]Kuan-Hua Tu, Hung-En Wang, Jie-Hong R. Jiang, Natalia Kushik, Nina Yevtushenko:
Homing Sequence Derivation With Quantified Boolean Satisfiability. IEEE Trans. Computers 71(3): 696-711 (2022) - [j22]Chia-Chih Chi, Jie-Hong R. Jiang:
Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 993-1005 (2022) - [c103]Chang-Jun Wang, Jie-Hong R. Jiang:
Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification. BioCAS 2022: 120-124 - [c102]Chun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang:
Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification. DAC 2022: 523-528 - [c101]Wan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang:
Language Equation Solving via Boolean Automata Manipulation. ICCAD 2022: 88:1-88:9 - [c100]Cheng-Han Hsieh, Jie-Hong R. Jiang:
Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability. IJCAI 2022: 1834-1842 - [c99]Tian-Fu Chen, Jie-Hong R. Jiang, Min-Hsiu Hsieh:
Partial Equivalence Checking of Quantum Circuits. QCE 2022: 594-604 - [c98]Hao-Ren Wang, Kuan-Hua Tu, Jie-Hong Roland Jiang, Christoph Scholl:
Quantifier Elimination in Stochastic Boolean Satisfiability. SAT 2022: 23:1-23:17 - 2021
- [j21]He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang:
SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 735-747 (2021) - [j20]Nian-Ze Lee, Jie-Hong R. Jiang:
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(5): 904-917 (2021) - [c97]Pei-Wei Chen, Yu-Ching Huang, Jie-Hong R. Jiang:
A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving. AAAI 2021: 3697-3706 - [c96]Nian-Ze Lee, Jie-Hong R. Jiang:
Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. AAAI 2021: 3877-3885 - [c95]Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang:
Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation. DAC 2021: 439-444 - [c94]He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton:
Deep Integration of Circuit Simulator and SAT Solver. DAC 2021: 877-882 - [c93]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c92]Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang:
Compatible Equivalence Checking of X-Valued Circuits. ICCAD 2021: 1-9 - [c91]He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko:
A Circuit-Based SAT Solver for Logic Synthesis. ICCAD 2021: 1-6 - 2020
- [c90]Pei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong Roland Jiang:
Circuit Learning for Logic Regression on High Dimensional Boolean Space. DAC 2020: 1-6 - [c89]Po-Chun Chien, Jie-Hong R. Jiang:
Time Multiplexing via Circuit Folding. DAC 2020: 1-6 - [c88]He-Teng Zhang, Jie-Hong R. Jiang:
SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. DAC 2020: 1-6 - [c87]Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee:
Engineering Change Order for Combinational and Sequential Design Rectification. DATE 2020: 726-731 - [c86]Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener:
Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. DATE 2020: 738-743 - [c85]Yu-Chou Lin, Jie-Hong R. Jiang:
Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. ICCAD 2020: 86:1-86:9 - [c84]Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets:
Symbolic Uniform Sampling with XOR Circuits. ICCAD 2020: 129:1-129:9 - [c83]Min Hao Peng, Fang Yu, Jie-Hong Roland Jiang:
Symbolic Gas Vulnerability Detection and Attack Synthesis. PACIS 2020: 107 - [i5]Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang:
Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation to a New Level. CoRR abs/2007.09304 (2020) - [i4]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [c82]Christoph Scholl, Jie-Hong Roland Jiang, Ralf Wimmer, Aile Ge-Ernst:
A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving. AAAI 2019: 1584-1591 - [c81]Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang:
An approximation algorithm to the optimal switch control of reconfigurable battery packs. ASP-DAC 2019: 577-584 - [c80]Yi-Fan Evan Chang, Ruei-Yang Huang, Jie-Hong R. Jiang:
Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. ASYNC 2019: 19-26 - [c79]Wei-Chih Huang, Jie-Hong Roland Jiang, François Fages, Franck Molina:
Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity. BioCAS 2019: 1-4 - [c78]Li-Cheng Chen, Jie-Hong R. Jiang:
A Cube Distribution Approach to QBF Solving and Certificate Minimization. CP 2019: 529-546 - [c77]Victor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang:
Comprehensive Search for ECO Rectification Using Symbolic Sampling. DAC 2019: 71 - [c76]Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang:
Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. DAC 2019: 73 - [c75]Po-Chun Chien, Jie-Hong R. Jiang:
Time-Frame Folding: Back to the Sequentiality. ICCAD 2019: 1-8 - [c74]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. ICCAD 2019: 1-8 - [c73]Zi-Jun Lin, Wei-Chih Huang, Jie-Hong Roland Jiang:
Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits. ISMVL 2019: 200-205 - [i3]Nian-Ze Lee, Jie-Hong R. Jiang:
Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. CoRR abs/1911.04112 (2019) - 2018
- [j19]Nian-Ze Lee, Jie-Hong R. Jiang:
Towards Formal Evaluation and Verification of Probabilistic Design. IEEE Trans. Computers 67(8): 1202-1216 (2018) - [c72]Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC 2018: 45:1-45:6 - [c71]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c70]He-Teng Zhang, Jie-Hong R. Jiang:
Cost-aware patch generation for multi-target function rectification of engineering change orders. DAC 2018: 96:1-96:6 - [c69]Chia-Chih Chi, Jie-Hong R. Jiang:
Logic synthesis of binarized neural networks for efficient circuit implementation. ICCAD 2018: 84 - [c68]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Canonicalization of threshold logic representation and its applications. ICCAD 2018: 85 - [c67]Chun-Han Lin, Fang Yu, Jie-Hong Roland Jiang, Tevfik Bultan:
Static detection of API call vulnerabilities in iOS executables. ICSE (Companion Volume) 2018: 394-395 - [c66]Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang:
Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection. IJCAI 2018: 1339-1345 - [c65]Hung-En Wang, Shih-Yu Chen, Fang Yu, Jie-Hong R. Jiang:
A symbolic model checking approach to the analysis of string and length constraints. ASE 2018: 623-633 - 2017
- [j18]Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong R. Jiang:
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1251-1264 (2017) - [c64]Chun-Hong Shih, Jie-Hong R. Jiang:
Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines. ASYNC 2017: 94-101 - [c63]Chun-Ning Lai, Jie-Hong R. Jiang, François Fages:
Recombinase-based genetic circuit optimization. BioCAS 2017: 1-4 - [c62]Chun-Ning Lai, Jie-Hong R. Jiang:
Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation. DAC 2017: 38:1-38:6 - [c61]Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang:
Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits. DAC 2017: 73:1-73:6 - [c60]Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang:
Sequential engineering change order under retiming and resynthesis. ICCAD 2017: 109-116 - [c59]Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang:
Solving Stochastic Boolean Satisfiability under Random-Exist Quantification. IJCAI 2017: 688-694 - [c58]Hung-En Wang, Kuan-Hua Tu, Jie-Hong R. Jiang, Natalia Kushik:
Homing Sequence Derivation with Quantified Boolean Satisfiability. ICTSS 2017: 230-242 - 2016
- [j17]Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang:
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(4): 598-610 (2016) - [j16]Valeriy Balabanov, Shuo-Ren Lin, Jie-Hong R. Jiang:
Flexibility and Optimization of QBF Skolem-Herbrand Certificates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1557-1568 (2016) - [j15]Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1797-1810 (2016) - [c57]Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl:
Clauses Versus Gates in CEGAR-Based 2QBF Solving. AAAI Workshop: Beyond NP 2016 - [c56]Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang:
String Analysis via Automata Manipulation with Logic Circuit Representation. CAV (1) 2016: 241-260 - [c55]Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang:
Design partitioning for large-scale equivalence checking and functional correction. DAC 2016: 23:1-23:6 - [c54]Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD 2016: 5 - [c53]Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton:
2QBF: Challenges and Solutions. SAT 2016: 453-469 - 2015
- [j14]Nina Yevtushenko, Khaled El-Fakih, Tiziano Villa, Jie-Hong R. Jiang:
Deriving Compositionally Deadlock-Free Components over Synchronous Automata Compositions. Comput. J. 58(11): 2793-2803 (2015) - [j13]Hui-Ju Katherine Chiang, François Fages, Jie-Hong Roland Jiang, Sylvain Soliman:
Hybrid Simulations of Heterogeneous Biochemical Models in SBML. ACM Trans. Model. Comput. Simul. 25(2): 14:1-14:22 (2015) - [c52]Valeriy Balabanov, Jie-Hong Roland Jiang, Mikolas Janota, Magdalena Widl:
Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs. AAAI 2015: 3694-3701 - [c51]Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang:
Scalable sequence-constrained retention register minimization in power gating design. DAC 2015: 130:1-130:6 - [c50]Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, François Fages:
Reconfigurable neuromorphic computation in biochemical systems. EMBC 2015: 937-940 - [c49]Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD 2015: 434-441 - [c48]Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang:
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD 2015: 442-449 - [c47]Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD 2015: 736-743 - [c46]Ting-Wei Chiang, Jie-Hong R. Jiang:
Property-Directed Synthesis of Reactive Systems from Safety Specifications. ICCAD 2015: 794-801 - [c45]Kuan-Hua Tu, Tzu-Chien Hsu, Jie-Hong R. Jiang:
QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving. SAT 2015: 343-359 - 2014
- [j12]Valeriy Balabanov, Hui-Ju Katherine Chiang, Jie-Hong R. Jiang:
Henkin quantifiers and Boolean formulae: A certification perspective of DQBF. Theor. Comput. Sci. 523: 86-100 (2014) - [c44]Hui-Ju Katherine Chiang, Jie-Hong R. Jiang, François Fages:
Building reconfigurable circuitry in a biochemical world. BioCAS 2014: 560-563 - [c43]Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang:
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. DAC 2014: 54:1-54:6 - [c42]Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC 2014: 192:1-192:6 - [c41]Nian-Ze Lee, Jie-Hong R. Jiang:
Towards formal evaluation and verification of probabilistic design. ICCAD 2014: 340-347 - [c40]Valeriy Balabanov, Magdalena Widl, Jie-Hong R. Jiang:
QBF Resolution Systems and Their Proof Complexities. SAT 2014: 154-169 - 2013
- [j11]Yi-Ting Chung, Jie-Hong Roland Jiang:
Functional Timing Analysis Made Fast and General. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1421-1434 (2013) - [j10]Tsung-Po Liu, Shuo-Ren Lin, Jie-Hong R. Jiang:
Software Workarounds for Hardware Errors: Instruction Patch Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1992-2003 (2013) - [c39]Hui-Ju Katherine Chiang, François Fages, Jie-Hong R. Jiang, Sylvain Soliman:
On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models. CMSB 2013: 192-205 - [c38]Kuan-Hua Tu, Jie-Hong R. Jiang:
Synthesis of feedback decoders for initialized encoders. DAC 2013: 49:1-49:6 - [c37]Georg Hofferek, Ashutosh Gupta, Bettina Könighofer, Jie-Hong Roland Jiang, Roderick Bloem:
Synthesizing multiple boolean functions using interpolation on a single proof. FMCAD 2013: 77-84 - [c36]Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li:
Automatic test pattern generation for delay defects using timed characteristic functions. ICCAD 2013: 91-98 - [c35]Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, Meng-Yen Li:
Encoding multi-valued functions for symmetry. ICCAD 2013: 771-778 - [i2]Georg Hofferek, Ashutosh Gupta, Bettina Könighofer, Jie-Hong Roland Jiang, Roderick Bloem:
Synthesizing Multiple Boolean Functions using Interpolation on a Single Proof. CoRR abs/1308.4767 (2013) - 2012
- [j9]Valeriy Balabanov, Jie-Hong R. Jiang:
Unified QBF certification and its applications. Formal Methods Syst. Des. 41(1): 45-65 (2012) - [j8]Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang:
Automatic Decoder Synthesis: Methods and Case Studies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1319-1331 (2012) - [j7]Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang:
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1723-1733 (2012) - [c34]Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang:
Clock rescheduling for timing engineering change orders. ASP-DAC 2012: 517-522 - [c33]Cheng-Shen Han, Jie-Hong Roland Jiang:
When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way. CAV 2012: 410-426 - [c32]Yi-Ting Chung, Jie-Hong Roland Jiang:
Functional timing analysis made fast and general. DAC 2012: 1055-1060 - [c31]De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng:
Compiling program control flows into biochemical reactions. ICCAD 2012: 361-368 - [c30]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Improving design verifiability by early RTL coverability analysis. MEMOCODE 2012: 25-32 - [c29]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Reducing test point overhead with don't-cares. MWSCAS 2012: 534-537 - [c28]Valeriy Balabanov, Hui-Ju Katherine Chiang, Jie-Hong Roland Jiang:
Henkin Quantifiers and Boolean Formulae. SAT 2012: 129-142 - 2011
- [j6]Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4(4): 34:1-34:23 (2011) - [c27]Valeriy Balabanov, Jie-Hong R. Jiang:
Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. CAV 2011: 149-164 - [c26]Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang:
Towards completely automatic decoder synthesis. ICCAD 2011: 389-395 - [c25]Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo:
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED 2011: 174-181 - 2010
- [j5]Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang:
To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59(4): 457-467 (2010) - [c24]Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang:
TRECO: dynamic technology remapping for timing engineering change orders. ASP-DAC 2010: 331-336 - [c23]Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang:
BooM: a decision procedure for boolean matching with abstraction and dynamic learning. DAC 2010: 499-504 - [c22]Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang:
Boolean matching of function vectors with strengthened learning. ICCAD 2010: 596-601 - [c21]Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang:
A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD 2010: 729-734 - [p1]Jie-Hong Roland Jiang, Tiziano Villa, Yves Crama, Peter L. Hammer:
Hardware Equivalence and Property Verification. Boolean Models and Methods 2010: 599-674
2000 – 2009
- 2009
- [c20]Jie-Hong R. Jiang:
Quantifier Elimination via Functional Composition. CAV 2009: 383-397 - [c19]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160 - [c18]Jie-Hong Roland Jiang, Hsuan-Po Lin, Wei-Lun Hung:
Interpolating functions from large Boolean relations. ICCAD 2009: 779-784 - 2008
- [c17]Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung:
Bi-decomposing large Boolean functions via interpolation and satisfiability solving. DAC 2008: 636-641 - [c16]Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee:
To SAT or not to SAT: Ashenhurst decomposition in a large scale. ICCAD 2008: 32-37 - [c15]Sz-Cheng Huang, Jie-Hong Roland Jiang:
A dynamic accuracy-refinement approach to timing-driven technology mapping. ICCD 2008: 538-543 - 2007
- [j4]Jie-Hong R. Jiang, Dah-Wei Chiou, Cheng-En Wu:
Quantum Mechanical Search and Harmonic Perturbation. Quantum Inf. Process. 6(5): 349-362 (2007) - [c14]Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233 - [c13]Jie-Hong Roland Jiang, Wei-Lun Hung:
Inductive equivalence checking under retiming and resynthesis. ICCAD 2007: 326-333 - [c12]Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits. PATMOS 2007: 148-159 - [i1]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007) - 2006
- [j3]Jie-Hong Roland Jiang, Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2674-2686 (2006) - 2005
- [c11]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423 - [c10]Jie-Hong Roland Jiang:
On Some Transformation Invariants Under Retiming and Resynthesis. TACAS 2005: 413-428 - 2004
- [c9]Jie-Hong Roland Jiang, Robert K. Brayton:
Functional Dependency for Verification Reduction. CAV 2004: 268-280 - [c8]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
On breakable cyclic definitions. ICCAD 2004: 411-418 - 2003
- [j2]Jie-Hong Roland Jiang, Robert K. Brayton:
On the verification of sequential equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 686-697 (2003) - [c7]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757 - 2002
- [c6]Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-179 - [c5]Jie-Hong Roland Jiang, Robert K. Brayton:
On the Verification of Sequential Equivalence. IWLS 2002: 307-314 - [c4]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - 2001
- [j1]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 251-260 (2001)
1990 – 1999
- 1999
- [c3]Jie-Hong Roland Jiang, Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry. ICCAD 1999: 520-525 - 1998
- [c2]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717 - 1997
- [c1]Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei:
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264
Coauthor Index
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