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ORCIDSaburo Muroga
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1990 – 1999
- 1999
[r24]Shin-ichi Minato, Saburo Muroga:
Binary Decision Diagrams. The VLSI Handbook 1999- [r23]Saburo Muroga:
Expressions of Logic Functions. The VLSI Handbook 1999 - [r22]Saburo Muroga:
Basic Theory of Logic Functions. The VLSI Handbook 1999 - [r21]Saburo Muroga:
Simplification of Logic Expressions. The VLSI Handbook 1999 - [r20]Saburo Muroga:
Logic Synthesis with AND and OR Gates in Two Levels. The VLSI Handbook 1999 - [r19]Saburo Muroga:
Sequential Networks with AND and OR Gates. The VLSI Handbook 1999 - [r18]Saburo Muroga:
Logic Properties of Transistor Circuits. The VLSI Handbook 1999 - [r17]Saburo Muroga:
Logic Synthesis with NAND (or NOR) Gates in Multi-levels. The VLSI Handbook 1999 - [r16]Saburo Muroga:
Logic Synthesis with a Minimum Number of Negative Gates. The VLSI Handbook 1999 - [r15]Saburo Muroga:
Logic Synthesizer by the Transduction Method. The VLSI Handbook 1999 - [r14]Saburo Muroga:
Emitter-Coupled Logic. The VLSI Handbook 1999 - [r13]Saburo Muroga:
CMOS. The VLSI Handbook 1999 - [r12]Saburo Muroga:
Full-Custom and Semi-Custom Design. The VLSI Handbook 1999 - [r11]Saburo Muroga:
Programmable Logic Devices. The VLSI Handbook 1999 - [r10]Saburo Muroga:
Mask-Programmable Gate Arrays. The VLSI Handbook 1999 - [r9]Saburo Muroga:
Field-Programmable Gate Arrays. The VLSI Handbook 1999 - [r8]Saburo Muroga:
Cell-Library Design Approach. The VLSI Handbook 1999 - [r7]Saburo Muroga:
Field-Programmable Gate Arrays. The VLSI Handbook 1999 - [r6]Yuichi Nakamura, Saburo Muroga:
Logic Synthesis with AND and OR Gates in Multi-levels. The VLSI Handbook 1999 - [r5]Naofumi Takagi, Charles R. Baugh, Saburo Muroga:
Multipliers. The VLSI Handbook 1999 - [r4]Naofumi Takagi, Saburo Muroga:
Dividers. The VLSI Handbook 1999 - [r3]Naofumi Takagi, Haruyuki Tago, Charles R. Baugh, Saburo Muroga:
Adders. The VLSI Handbook 1999 - [r2]Kazuo Yano, Saburo Muroga:
Pass Transistors. The VLSI Handbook 1999 - [r1]Ko Yoshikawa
, Saburo Muroga:
Logic Synthesizer with Optimizations in Two Phases. The VLSI Handbook 1999 - 1996
- [j34]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Design of logic circuits with wired-logic utilizing transduction method. Syst. Comput. Jpn. 27(11): 19-28 (1996) - [j33]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Optimization methods for look-up table-type FPGAs based on permissible functions. Syst. Comput. Jpn. 27(12): 92-101 (1996) - 1995
- [c12]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC 1995 - 1993
- [c11]Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga:
A Shared Memory Parallel Algorithm for Logic Synthesis. VLSI Design 1993: 317-322 - 1991
- [j32]Saburo Muroga:
Computer-Aided Logic Synthesis for VLSI Chips. Adv. Comput. 32: 1-103 (1991) - [j31]Sung Je Hong, Saburo Muroga:
Absolute Minimization of Completely Specified Switching Functions. IEEE Trans. Computers 40(1): 53-65 (1991) - [c10]Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita:
A Resynthesis Approach for Network Optimization. DAC 1991: 458-463 - [c9]Johnson Chan Limqueco, Saburo Muroga:
Logic Optimization of MOS Networks. DAC 1991: 464-469 - 1990
- [c8]Kuang-Chien Chen, Saburo Muroga:
Timing Optimization for Multi-Level Combinational Networks. DAC 1990: 339-344 - [c7]Johnson Chan Limqueco, Saburo Muroga:
SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. ICCD 1990: 282-285
1980 – 1989
- 1989
- [j30]Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney:
The Transduction Method-Design of Logic Networks Based on Permissible Functions. IEEE Trans. Computers 38(10): 1404-1424 (1989) - [c6]Kuang-Chien Chen, Saburo Muroga:
SYLON-DREAM: a multi-level network synthesizer. ICCAD 1989: 552-555 - 1988
- [j29]Hung Chi Lai, Saburo Muroga:
Design of MOS networks in single-rail input logic for incompletely specified functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 339-345 (1988) - [c5]Kuang-Chien Chen, Saburo Muroga:
Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD 1988: 474-477 - 1987
- [j28]Hung Chi Lai, Saburo Muroga:
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables. IEEE Trans. Computers 36(2): 157-166 (1987) - [j27]Robert Brian Cutler, Saburo Muroga:
Derivation of Minimal Sums for Completely Specified Functions. IEEE Trans. Computers 36(3): 277-292 (1987) - 1986
- [j26]Yahiko Kambayashi, Saburo Muroga:
Properties of Wired Logic. IEEE Trans. Computers 35(6): 550-563 (1986) - 1985
- [j25]Ming Huei Young, Saburo Muroga:
Minimal covering problem and PLA minimization. Int. J. Parallel Program. 14(6): 337-364 (1985) - [j24]Ming Huei Young, Saburo Muroga:
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. IEEE Trans. Computers 34(6): 523-541 (1985) - 1984
- [j23]Ging-Shung Yu, Saburo Muroga:
Parallel multipliers with NOR gates based on G-minimum adders. Int. J. Parallel Program. 13(2): 111-121 (1984) - 1983
- [j22]Akito Sakurai, Saburo Muroga:
Parallel Binary Adders with a Minimum Number of Connections. IEEE Trans. Computers 32(10): 969-976 (1983) - 1982
- [j21]Hung Chi Lai, Saburo Muroga:
Logic Networks of Carry-Save Adders. IEEE Trans. Computers 31(9): 870-882 (1982) - 1980
- [j20]Robert Brian Cutler, Saburo Muroga:
Useless prime implicants of incompletely specified multiple-output switching functions. Int. J. Parallel Program. 9(4): 337-350 (1980)
1970 – 1979
- 1979
- [j19]Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga:
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. IEEE Trans. Computers 28(1): 76-85 (1979) - [j18]Robert Brian Cutler, Saburo Muroga:
Comments on "Generalization of Consensus Theory and Application to the Minimization of Boolean Functions". IEEE Trans. Computers 28(7): 542-543 (1979) - [j17]Hung Chi Lai, Saburo Muroga:
Minimum Parallel Binary Adders with NOR (NAND) Gates. IEEE Trans. Computers 28(9): 648-659 (1979) - [j16]Robert Brian Cutler, Saburo Muroga:
Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions". IEEE Trans. Computers 28(11): 874-875 (1979) - 1976
- [j15]Saburo Muroga, Hung Chi Lai:
Minimization of Logic Networks Under a Generalized Cost Function. IEEE Trans. Computers 25(9): 893-907 (1976) - 1974
- [j14]Hung Chi Lai, Tomoyasu Nakagawa, Saburo Muroga:
Redundancy check technique for designing optimal networks by branch-and-bound method. Int. J. Parallel Program. 3(3): 251-271 (1974) - [j13]Tso-Kai Liu, Keith R. Hohulin, Lih-Er Shiau, Saburo Muroga:
Optimal One-Bit Full Adders With Different Types of Gates. IEEE Trans. Computers 23(1): 63-70 (1974) - 1972
- [j12]Toshihide Ibaraki, Tso-Kai Liu, Charles R. Baugh, Saburo Muroga:
An implicit enumeration program for zero-one integer programming. Int. J. Parallel Program. 1(1): 75-92 (1972) - [j11]Charles R. Baugh, C. S. Chandersekaran, Richard S. Swee, Saburo Muroga:
Optimal Networks of NOR-OR Gates for Functions of Three Variables. IEEE Trans. Computers 21(2): 153-160 (1972) - [j10]Saburo Muroga, Toshihide Ibaraki:
Design of Optimal Switching Networks by Integer Programming. IEEE Trans. Computers 21(6): 573-582 (1972) - 1971
- [b1]Saburo Muroga:
Threshold logic and its applications. Wiley 1971, ISBN 978-0-471-62530-8, pp. I-XIV, 1-478 - [j9]Charles R. Baugh, Toshihide Ibaraki, Saburo Muroga:
Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks. Oper. Res. 19(4): 1090-1096 (1971) - [j8]Toshihide Ibaraki, Saburo Muroga:
Synthesis of Networks with a Minimum Number of Negative Gates. IEEE Trans. Computers 20(1): 49-58 (1971) - 1970
- [j7]Saburo Muroga, Teiichi Tsuboi, Charles R. Baugh:
Enumeration of Threshold Functions of Eight Variables. IEEE Trans. Computers 19(9): 818-825 (1970) - [j6]Toshihide Ibaraki, Saburo Muroga:
Adaptive Linear Classifier by Linear Programming. IEEE Trans. Syst. Sci. Cybern. 6(1): 53-62 (1970)
1960 – 1969
- 1966
- [j5]Saburo Muroga, Iwao Toda:
Lower Bound of the Number of Threshold Functions. IEEE Trans. Electron. Comput. 15(5): 805-806 (1966) - 1965
- [j4]Saburo Muroga:
Generation and Asymmetry of Self-Dual Threshold Functions. IEEE Trans. Electron. Comput. 14(2): 125-136 (1965) - [j3]Saburo Muroga:
Lower Bounds of the Number of Threshold Functions and a Maximum Weight. IEEE Trans. Electron. Comput. 14(2): 136-148 (1965) - 1962
- [c4]Saburo Muroga:
Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight. SWCT 1962: 169-184 - 1961
- [c3]Saburo Muroga:
Functional forms of majority functions and a necessary and sufficient condition for their realizability. SWCT 1961: 39-46 - [c2]Calvin C. Elgot, Saburo Muroga:
Two problems on threshold functions. SWCT 1961: 166
1950 – 1959
- 1959
- [j2]Saburo Muroga, Kensuke Takashima:
The Parametron Digital Computer MUSASINO-1. IRE Trans. Electron. Comput. 8(3): 308-316 (1959) - [c1]Saburo Muroga:
The principle of majority decision logical elements and the complexity of their circuits. IFIP Congress 1959: 400-406 - 1957
- [j1]Saburo Muroga:
On the capacity of a noisy continuous channel. IRE Trans. Inf. Theory 3(1): 44-51 (1957)
Coauthor Index
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