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ORCIDMasayuki Hiromoto
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2020 – today
- 2023
[c31]So Hasegawa, Masayuki Hiromoto, Akira Nakagawa
, Yuhei Umeda:
Improving Predicate Representation in Scene Graph Generation by Self-Supervised Learning. WACV 2023: 2739-2748- 2022
- [j18]Masayuki Hiromoto, Hisanao Akima, Teruo Ishihara, Takuji Yamamoto:
SimpleZSL: Extremely Simple and Fast Zero-Shot Learning with Nearest Neighbor Classifiers. IEICE Trans. Inf. Syst. 105-D(2): 396-405 (2022) - 2020
- [c30]Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato:
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CVPR 2020: 9400-9409 - [i1]Song Bian, Tianchen Wang, Masayuki Hiromoto, Yiyu Shi, Takashi Sato:
ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. CoRR abs/2003.05328 (2020)
2010 – 2019
- 2019
- [j17]Song Bian, Masayuki Hiromoto, Takashi Sato:
Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(2): 430-439 (2019) - [j16]Chase Cook, Hengyang Zhao, Takashi Sato, Masayuki Hiromoto, Sheldon X.-D. Tan:
GPU-based Ising computing for solving max-cut combinatorial optimization problems. Integr. 69: 335-344 (2019) - [c29]Song Bian, Masayuki Hiromoto, Takashi Sato:
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. ASP-DAC 2019: 621-626 - [c28]Song Bian, Masayuki Hiromoto, Takashi Sato:
Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. DAC 2019: 113 - [c27]Song Bian, Masayuki Hiromoto, Takashi Sato:
DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. DATE 2019: 1739-1744 - 2018
- [j15]Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato:
Area Efficient Annealing Processor for Ising Model without Random Number Generator. IEICE Trans. Inf. Syst. 101-D(2): 314-323 (2018) - [j14]Masayuki Hiromoto, Motoki Yoshinaga, Takashi Sato:
MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1035-1044 (2018) - [j13]Satoshi Yamamori, Masayuki Hiromoto, Takashi Sato:
Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1092-1100 (2018) - [j12]Yuya Fujita, Masayuki Hiromoto, Takashi Sato:
PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. IEEE Trans. Biomed. Eng. 65(1): 189-198 (2018) - [j11]Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato:
Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 602-606 (2018) - [c26]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC 2018: 631-636 - [c25]Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato:
Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. CVPR Workshops 2018: 616-624 - [c24]Song Bian, Masayuki Hiromoto, Takashi Sato:
DWE: decrypting learning with errors with errors. DAC 2018: 3:1-3:6 - [c23]Yuya Fujita, Masayuki Hiromoto, Takashi Sato:
Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. EMBC 2018: 3024-3027 - [c22]Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato:
Enhancing the solution quality of hardware ising-model solver via parallel tempering. ICCAD 2018: 70 - [c21]Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED 2018: 251-256 - 2017
- [j10]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1464-1472 (2017) - [j9]Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2797-2806 (2017) - [c20]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Efficient circuit failure probability calculation along product lifetime considering device aging. ASP-DAC 2017: 93-98 - [c19]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC 2017: 66:1-66:6 - [c18]Song Bian, Masayuki Hiromoto, Takashi Sato:
SCAM: Secured content addressable memory based on homomorphic encryption. DATE 2017: 984-989 - [c17]Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED 2017: 426-431 - 2016
- [j8]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1390-1399 (2016) - [j7]Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1400-1409 (2016) - [c16]Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato:
Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS 2016: 234-239 - [c15]Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato:
Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. CVPR Workshops 2016: 870-876 - [c14]Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI 2016: 203-208 - [c13]Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. ISCAS 2016: 2619-2622 - [c12]Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato:
Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED 2016: 307-312 - 2015
- [j6]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. IEICE Trans. Electron. 98-C(7): 741-750 (2015) - [c11]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. DATE 2015: 549-554 - 2014
- [j5]Hirofumi Shimizu, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Automation of Model Parameter Estimation for Random Telegraph Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2383-2392 (2014) - [c10]Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato:
Variability in device degradations: Statistical observation of NBTI for 3996 transistors. ESSDERC 2014: 218-221 - 2013
- [c9]Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi:
Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE 2013: 535-540 - 2010
- [j4]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2524-2532 (2010) - [c8]Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato:
A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC 2010: 248-253
2000 – 2009
- 2009
- [j3]Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. Inf. Media Technol. 4(2): 250-260 (2009) - [j2]Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
An Asynchronous IEEE-754-standard Single-precision Floating-point Divider for FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 2: 103-113 (2009) - [j1]Masayuki Hiromoto, Hiroki Sugano, Ryusuke Miyamoto:
Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features. IEEE Trans. Circuits Syst. Video Technol. 19(1): 41-52 (2009) - [c7]Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye:
Coarse-grained dynamically reconfigurable architecture with flexible reliability. FPL 2009: 186-192 - [c6]Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi, Yukihiro Nakamura:
Hot-Swapping architecture extension for mitigation of permanent functional unit faults. FPL 2009: 578-581 - [c5]Masayuki Hiromoto, Ryusuke Miyamoto:
Hardware architecture for high-accuracy real-time pedestrian detection with CoHOG features. ICCV Workshops 2009: 894-899 - [c4]Masayuki Hiromoto, Ryusuke Miyamoto:
Cascade Classifier Using Divided CoHOG Features for Rapid Pedestrian Detection. ICVS 2009: 53-62 - [c3]Ryoji Kadota, Hiroki Sugano, Masayuki Hiromoto, Hiroyuki Ochi, Ryusuke Miyamoto, Yukihiro Nakamura:
Hardware Architecture for HOG Feature Extraction. IIH-MSP 2009: 1330-1333 - [c2]Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura:
Dynamic rate control for media streaming in high-speed mobile networks. WCNC 2009: 2983-2988 - 2007
- [c1]Masayuki Hiromoto, Kentaro Nakahara, Hiroki Sugano, Yukihiro Nakamura, Ryusuke Miyamoto:
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features. CVPR 2007
Coauthor Index
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