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ORCIDKunihiro Asada
- > Home > Persons > Kunihiro Asada
Publications
- 2022
[j70]Tetsuya Iizuka, Meikan Chin, Toru Nakura, Kunihiro Asada:
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. IEICE Trans. Electron. 105-C(10): 544-551 (2022)- 2021
- [c135]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Kunihiro Asada:
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper. ICICDT 2021: 1-4 - 2019
- [j69]Tetsuya Iizuka, Kai Xu, Xiao Yang, Toru Nakura, Kunihiro Asada:
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. IEICE Electron. Express 16(19): 20190390 (2019) - [j68]Daigo Takahashi
, Tetsuya Iizuka, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada:
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. IEEE Trans. Instrum. Meas. 68(7): 2519-2530 (2019) - [j67]Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 11-19 (2019) - 2018
- [j66]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. J. Electron. Test. 34(2): 147-161 (2018) - [j65]Kunihiro Asada, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda:
Time-domain approach for analog circuits in deep sub-micron LSI. IEICE Electron. Express 15(5) (2018) - [j64]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(2): 410-424 (2018) - [j63]Toru Nakura, Tsukasa Kagaya, Tetsuya Iizuka, Kunihiro Asada:
Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. IEICE Trans. Electron. 101-C(4): 218-223 (2018) - [j62]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. IEICE Trans. Electron. 101-C(4): 292-298 (2018) - [j61]Nguyen Ngoc Mai Khanh, Shigeru Nakajima, Tetsuya Iizuka, Yoshio Mita, Kunihiro Asada:
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation. IEEE Trans. Instrum. Meas. 67(4): 745-753 (2018) - [c134]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture. MWSCAS 2018: 408-411 - [c133]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. VLSI-SoC (Selected Papers) 2018: 1-13 - [c132]Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. VLSI-SoC 2018: 55-58 - 2017
- [j60]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(1): 200-209 (2017) - [j59]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. IEICE Trans. Electron. 100-C(9): 736-745 (2017) - [j57]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A PLL Compiler from Specification to GDSII. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2741-2749 (2017) - [c131]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. ASP-DAC 2017: 23-24 - [c130]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
CMOS-on-quartz pulse generator for low power applications. ASP-DAC 2017: 29-30 - [c129]Kai Xu, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
High Spatial Resolution Detection Method for Point Light Source in Scintillator. Computational Imaging 2017: 18-23 - [c128]Naoki Terao, Toru Nakura, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Extension of power supply impedance emulation method on ATE for multiple power domain. ETS 2017: 1-2 - [c127]Takaaki Ito, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. ICECS 2017: 1-4 - [c126]Ryuichi Enomoto, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. ICECS 2017: 231-234 - [c125]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. ICECS 2017: 318-321 - [c124]Xiao Yang, Kai Xu, Tetsuya Iizuka, Toru Nakura, Hongbo Zhu, Kunihiro Asada:
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. IEEE SENSORS 2017: 1-3 - [c123]Parit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Impulse signal generator based on current-mode excitation and transmission line resonator. NEWCAS 2017: 257-260 - 2016
- [j53]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. J. Circuits Syst. Comput. 25(3): 1640017:1-1640017:16 (2016) - [c122]Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. A-SSCC 2016: 313-316 - [c121]Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. DATE 2016: 517-522 - [c120]Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada:
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. ESSCIRC 2016: 301-304 - [c118]Nguyen Ngoc Mai Khanh, Rimon Ikeno, Takahiro J. Yamaguchi, Tetsuya Iizuka, Kunihiro Asada:
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration. ICECS 2016: 29-32 - [c117]Masahiro Kano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Resonant power supply noise reduction using a triangular active charge injection. ICECS 2016: 113-116 - [c114]Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. ITC 2016: 1-8 - 2015
- [j50]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs. IEEE Trans. Instrum. Meas. 64(4): 840-848 (2015) - [c112]Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. A-SSCC 2015: 1-4 - [c110]Xiao Yang, Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. DDECS 2015: 131-136 - [c109]Takashi Toi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. NORCAS 2015: 1-4 - 2014
- [j48]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(8): 1688-1698 (2014) - [c101]Nguyen Ngoc Mai Khanh, Tetsuya Iizuka, Akihiko Sasaki, Makoto Yamada, Osamu Morita, Kunihiro Asada:
High-resolution measurement of magnetic field generated from cryptographic LSIs. SAS 2014: 111-114 - 2013
- [j45]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2458-2466 (2013) - [c100]Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada:
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design. ASP-DAC 2013: 255-260 - [c99]Tetsuya Iizuka, Satoshi Miura, Yohei Ishizone, Yoshimichi Murakami, Kunihiro Asada:
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC. CICC 2013: 1-4 - [c98]Tetsuya Iizuka, Teruki Someya, Toru Nakura, Kunihiro Asada:
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. CICC 2013: 1-4 - [c96]Norihito Tohge, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
A Pulse Width controlled PLL and its automated design flow. ICECS 2013: 5-8 - [c94]Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. ISPD 2013: 69-76 - 2012
- [j41]Tetsuya Iizuka, Kunihiro Asada:
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator. IEICE Trans. Electron. 95-C(4): 627-634 (2012) - [j39]Tetsuya Iizuka, Satoshi Miura, Ryota Yamamoto, Yutaka Chiba, Shunichi Kubo, Kunihiro Asada:
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology. IEICE Trans. Electron. 95-C(4): 661-667 (2012) - [j38]Kazutoshi Kodama, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. IEICE Trans. Electron. 95-C(12): 1857-1863 (2012) - [c90]Toru Nakura, Tetsuya Iizuka, Kunihiro Asada:
Impact of All-Digital PLL on SoC Testing. Asian Test Symposium 2012: 252-257 - [c89]Toru Nakura, Yoshio Mita, Tetsuya Iizuka, Kunihiro Asada:
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. CICC 2012: 1-4 - 2011
- [j36]Tetsuya Iizuka, Kunihiro Asada:
All-digital ramp waveform generator for two-step single-slope ADC. IEICE Electron. Express 8(1): 20-25 (2011) - [j33]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. IEICE Trans. Electron. 94-C(4): 487-494 (2011) - [j30]Shingo Mandai, Toru Nakura, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Cascaded Time Difference Amplifier with Differential Logic Delay Cell. IEICE Trans. Electron. 94-C(4): 654-662 (2011) - [j29]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. IEICE Trans. Electron. 94-C(6): 1098-1104 (2011) - [j26]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation. J. Next Gener. Inf. Technol. 2(4): 1-9 (2011) - [c83]Jaehyun Jeong, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. ASP-DAC 2011: 79-80 - [c80]Tetsuya Iizuka, Kunihiro Asada:
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator. DDECS 2011: 115-120 - [c78]Kazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada:
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme. ESSCIRC 2011: 399-402 - 2010
- [c68]Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. DDECS 2010: 167-172 - [c66]Tetsuya Iizuka, Jaehyun Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. ESSCIRC 2010: 182-185 - [c65]Shingo Mandai, Tetsuya Iizuka, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Time-to-digital converter based on time difference amplifier with non-linearity calibration. ESSCIRC 2010: 266-269 - 2007
- [j20]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 716-720 (2007) - [c51]Kenichiro Kurihara, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS. ICECS 2007: 1296-1299 - [c50]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
OPC-Friendly De-Compaction with Timing Constraints for Standard Cell Layouts. ISQED 2007: 776-781 - 2006
- [c46]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-driven cell layout de-compaction for yield optimization by critical area minimization. DATE 2006: 884-889 - [c43]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Timing-Driven Redundant Contact Insertion for Standard Cell Yield Enhancement. ICECS 2006: 704-707 - [c38]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells. ISCAS 2006 - 2005
- [j10]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1957-1963 (2005) - [j8]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3485-3491 (2005) - [c35]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact minimum-width transistor placement without dual constraint for CMOS cells. ACM Great Lakes Symposium on VLSI 2005: 74-77 - 2004
- [c31]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154 - [c27]Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. ISQED 2004: 377-380
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