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"Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault ..."

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (2005)

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DOI: 10.1093/IETFEC/E88-A.7.1957

access: closed

type: Journal Article

metadata version: 2020-04-11

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Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1957-1963 (2005)

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