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ORCIDIEEE Journal of Solid-State Circuits, Volume 32
Volume 32, Number 1, January 1997
- Kostas Vavelidis, Yannis P. Tsividis, Frank Op't Eynde, Yannis Papananos:
Six-terminal MOSFET's: modeling and applications in highly linear, electronically tunable resistors. 4-12 - Mats Høvin, Alf Olsen, Tor Sverre Lande
, Chris Toumazou:
Delta-sigma modulators using frequency-modulated intermediate values. 13-22 - Steven L. Garverick, Michael L. Nagy, Naresh K. Rao, David K. Hartsfield, Arvind Purushotham:
A capacitive sensing integrated circuit for detection of micromotor critical angles. 23-30 - Hiroyuki Yamada, Masanori Tsunotani, Fumiyasu Kaneyama, Shouhei Seki:
20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems. 31-37 - Ming-Dou Ker, Hun-Hsien Chang, Chung-Yu Wu:
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs. 38-51 - Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina:
A 0.25-μm CMOS 0.9-V 100-MHz DSP core. 52-61 - Jiren Yuan, Christer Svensson:
New single-clock CMOS latches and flipflops with improved speed and power savings. 62-69 - S. M. Rezaul Hasan, Chakaravarty D. Rajagopal:
Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic. 70-78 - Young-Hee Kim, Jae-Yoon Sim, Hong June Park, Jae-Ik Doh, Kun-Woo Park, Hyun-Woong Chung, Jong-Hoon Oh, Choon-Sik Oh, Seung-Han Ahn:
Analysis and prevention of DRAM latch-up during power-on. 79-85 - Daisaburo Takashima, Yukihito Oowaki:
A novel power-off mode for a battery-backup DRAM. 86-91 - Ho-Jun Song, Jung-Pill Kim, Jae-Jin Lee, Jong-Hoon Oh, Seung-Han Ahn, Inseok Hwang:
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM. 92-99 - Carlo Fiocchi, Guido Torelli, Stefano Ghezzi, Marco Maccarrone:
Program load adaptive voltage generator for flash memories. 100-104 - Toshio Sunaga, Koji Hosokawa, Yutaka Nakamura, Manabu Ichinose, Yasuyuki Igarashi:
An eight-bit prefetch circuit for high-bandwidth DRAM's. 105-110 - Scott K. Reynolds:
A DC-DC converter for short-channel CMOS technologies. 111-113 - Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su:
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. 114-118 - J. H. Lou, James B. Kuo:
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI. 119-121 - Jason P. Hurst, Adit D. Singh:
A differential built-in current sensor design for high-speed IDDQ testing. 122-125 - Steven Galecki:
Multiphase sine-shaper circuit. 126-129 - A. K. Gupta, James W. Haslett, Fred N. Trofimenkoff:
BiCMOS adjustable linear current mirror. 130-134 - Nikos Haralabidis, Dimitris Loukas, Konstantinos Misiakos, Stavros Katsafouros:
A transimpedance CMOS multichannel amplifier with a 50 Ω-wide output range buffer for high counting rate applications. 135-138
Volume 32, Number 2, February 1997
- Qiuting Huang:
A MOSFET-only continuous-time bandpass filter. 147-158 - Chung-Yu Wu, Shuo-Yuan Hsiao:
The design of a 3-V 900-MHz CMOS bandpass amplifier. 159-168 - Laszlo Moldovan, Hua Harry Li:
A rail-to-rail, constant gain, buffered op-amp for real time video applications. 169-176 - Philippe Venier, Alessandro Mortara, Xavier Arreguit, Eric A. Vittoz:
An integrated cortical layer for orientation enhancement. 177-186 - Sunetra K. Mendis, Sabrina E. Kemeny, Russell C. Gee, Bedabrata Pain, Craig O. Staller, Quiesup Kim, Eric R. Fossum:
CMOS active pixel image sensors for highly integrated imaging systems. 187-197 - Michael L. Simpson, Charles L. Britton Jr., Alan L. Wintenberg, Glenn R. Young:
An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter. 198-205 - Zhongde Wang, Graham A. Jullien, William C. Miller, Jinghong Wang, Sami S. Bizzan:
Fast adders using enhanced multiple-output domino logic. 206-214 - Keiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino:
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. 215-221 - William Williamson III, Steven B. Enquist, David H. Chow, Howard L. Dunlap, Suresh Subramaniam, Peiming Lei, Gary H. Bernstein, Barry K. Gilbert:
12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates. 222-231 - H. Kato, M. Matsui, K. Sato, H. Shibata, K. Hashimoto, T. Ootani, K. Ochii:
SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober. 232-237 - Kimmo Koli, Kari Halonen:
A fully differential class-AB switched-current integrator for signal processing. 238-244 - Eyad Abou-Allam, Ezz I. El-Masry:
A 200 MHz steered current operational amplifier in 1.2-μm CMOS technology. 245-249 - Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst:
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. 250-253 - Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund:
A reduced-area low-power low-voltage single-ended differential pair. 254-257 - Katsuji Kimura:
A bipolar low-voltage quarter-square multiplier with a resistive-input based on the bias offset technique. 258-266 - Richard J. Reay, Klaas B. Klaassen, Calvin S. Nomura:
A resonant switching write driver for magnetic recording. 267-269 - Rohit Mittal, Kimberly C. Bracken, L. Richard Carley, David J. Allstot:
A low-power backward equalizer for DFE read-channel applications. 270-273 - Raquel Pérez-Aloe, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio, José M. Valverde, Guido Torelli, Alexander H. Reyes, Franco Maloberti:
Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations. 274-278 - Alireza Moini, Abdesselam Bouzerdoum, Kamran Eshraghian, Andre Yakovleff, Xuan Thong Nguyen, Andrew J. Blanksby, Richard Beare, Derek Abbott, Robert Eugene Bogner:
An insect vision-based motion detection chip. 279-284 - Orly Yadid-Pecht, Bedabrata Pain, Craig O. Staller, Christopher Clark, Eric R. Fossum:
CMOS active pixel sensor star tracker with regional electronic shutter. 285-288 - Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. 289-291 - Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. 292 - Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko:
Authors Reply. 293
Volume 32, Number 3, March 1997
- Kwang Young Kim, Naoya Kusayanagi, Asad A. Abidi:
A 10-b, 100-MS/s CMOS A/D converter. 302-311 - Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger:
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. 312-320 - Stephen Au, Bosco H. Leung:
A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops. 321-328 - Ichiro Fujimori, Kazuo Koyama, David Trager, Fred Tam, Lorenzo Longo:
A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range. 329-336 - Donald C. Thelen Jr., Dahlon D. Chu:
A low noise readout detector circuit for nanoampere sensor applications. 337-348 - Jean-Baptiste Bégueret, Mohammed Reda Benbrahim, Zhiqun Li, Francis Rodes, Jean Paul Dom:
Converters dedicated to long-term monitoring of strain gauge transducers. 349-356 - John R. Long, Miles A. Copeland:
The modeling, characterization, and design of monolithic inductors for silicon RF IC's. 357-369 - Peter R. Kinget, Michiel S. J. Steyaert:
A 1-GHz CMOS up-conversion mixer. 370-376 - Gilles van Ruymbeke, Christian C. Enz, François Krummenacher, Michel J. Declercq:
A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique. 377-387 - Zhong Yuan Chang, Didier Haspeslagh, Johan Verfaillie:
A highly linear CMOS Gm-C bandpass filter with on-chip frequency tuning. 388-397 - David A. Johns, Daniel Essig:
Integrated circuits for data transmission over twisted-pair channels. 398-406 - Thaddeus J. Gabara, Wilhelm C. Fischer, John Harrington, William W. Troutman:
Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers. 407-418 - Thaddeus J. Gabara, Wilhelm C. Fischer:
Capacitive coupling and quantized feedback applied to conventional CMOS technology. 419-427 - James S. Caravella:
A low voltage SRAM for embedded applications. 428-432 - Renu Mehra, Lisa M. Guerra, Jan M. Rabaey:
A partitioning scheme for optimizing interconnect power. 433-443 - Yasuhiko Hagihara, Shigeto Inui, Fuyuki Okamoto, Masato Nishida, Toshihiko Nakamura, Hachiro Yamada:
Floating-point datapaths with online built-in self speed test. 444-449 - Ravinder S. Kajley, Paul J. Hurst, James E. C. Brown:
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture. 450-459 - Kiyoshi Okamoto, Takuya Jinbo, Toshiyuki Araki, Yasuo Iizuka, Hiromasa Nakajima, Minoru Takahata, Hisashi Inoue, Shun-ichi Kurohmaru, Tomonori Yonezawa, Kunitoshi Aono:
A DSP for DCT-based and wavelet-based video codecs for consumer applications. 460-467 - Jun Rim Choi, Lak Hyun Jang, Seong Wook Jung, Jin Ho Choi:
Structured design of a 288-tap FIR filter by optimized partial product tree compression. 468-476 - Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. 477-482
Volume 32, Number 4, April 1997
- Klaas-Jan de Langen, Rudy G. H. Eschauzier, Gert J. A. van Dijk, Johan H. Huijsing:
A 1-GHz bipolar class-AB operational amplifier with multipath nested Miller compensation for 76-dB gain. 488-498 - Iuri Mehr, David R. Welland:
A CMOS continuous-time Gm-C filter for PRML read channel applications at 150 Mb/s and beyond. 499-513 - Bang-Sup Song, David C. Soo:
NRZ timing recovery technique for band-limited channels. 514-520 - Mohammad Madihian, Emmanuel Bak, Hiroshi Yoshida, Hiroshi Hirabayashi, Kyotaka Imai, Yasushi Kinoshita, Tohru Yamazaki, Laurent Desclos:
A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks. 521-525 - Chin-Fong Chiu, Chung-Yu Wu:
The design of rotation-invariant pattern recognition using the silicon retina. 526-534 - Antonio J. Montalvo, Ronald S. Gyurcsik, John J. Paulos:
An analog VLSI neural network with on-chip perturbation learning. 535-543 - Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama:
Phase-correcting feedback system for class E power amplifier. 544-549 - Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III:
The delay vernier pattern generation technique. 551-562 - Fang-Shi Lai, Wei Hwang:
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems. 563-573 - Patrik Larsson:
Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance. 574-576 - Wouter A. Serdijn, Martijn Broest, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund:
A low-voltage ultra-low-power translinear integrator for audio filter applications. 577-581 - Howard C. Yang, Lance K. Lee, Ramon S. Co:
A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation. 582-586 - Anna M. Murphy, Shinichi Tsutsumi, Peter Gaussen:
A low-power, low-cost bipolar GPS receiver chip. 587-591 - José Francisco López, Roberto Sarmiento, Kamran Eshraghian, Antonio Núñez:
Noise margin enhancement in GaAs ROM's using current mode logic. 592-597 - Juan M. Casalta, Xavier Aragonès, Antonio Rubio:
Substrate coupling evaluation in BiCMOS technology. 598-603 - Muhammad E. S. Elrabaa, Mohamed I. Elmasry, Duljit S. Malhi:
Low-power BiCMOS circuits for high-speed interchip communication. 604-609 - Wing C. Leung:
A high-performance, low-power complementary coupled BiCMOS circuit. 610-612
Volume 32, Number 5, May 1997
- Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe:
Limitations and challenges of multigigabit DRAM chip design. 624-634 - Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. 635-641 - Kyu-Chan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-Hoon Sim, Sang-Bo Lee, Byung-Sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo, Soo-In Cho:
Low-voltage, high-speed circuit designs for gigabit DRAMs. 642-648 - Hiroshige Hirano, Toshiyuki Honda, Nobuyuki Moriwaki, Tetsuji Nakakuma, Atsuo Inoue, George Nakane, Shigeo Chaya, Tatsumi Sumi:
2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell. 649-654 - Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya:
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. 655-661 - Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi:
A compact on-chip ECC for low cost flash memories. 662-669 - Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto:
A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. 670-680 - Stefanos Sidiropoulos, Mark Horowitz:
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. 681-690 - Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim:
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. 691-700 - William Redman-White:
A high bandwidth constant gm and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems. 701-712 - Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis:
A mixed-signal RAM decision-feedback equalizer for disk drives. 713-721 - Paul J. Chang, Ahmadreza Rofougaran, Asad A. Abidi:
A CMOS channel-select filter for a direct-conversion wireless receiver. 722-729 - Behzad Razavi:
A 2-GHz 1.6-mW phase-locked loop. 730-735 - Jan Craninckx, Michiel S. J. Steyaert:
A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors. 736-744 - Derek K. Shaeffer, Thomas H. Lee:
A 1.5-V, 1.5-GHz CMOS low noise amplifier. 745-759 - Seog-Jun Lee, Beomsup Kim, Kwyro Lee:
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application. 760-765 - Tadao Nakagawa, Hideyuki Nosaka:
A direct digital synthesizer with interpolation circuits. 766-770
Volume 32, Number 6, June 1997
- Feng Chen, Bosco Leung:
A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input. 774-782 - Shahriar Rabii, Bruce A. Wooley:
A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS. 783-796 - Peter J. Black, Teresa H.-Y. Meng:
A 1-Gb/s, four-state, sliding block Viterbi decoder. 797-805 - Peter Nilsson, Mats Torkelson:
A custom digital intermediate frequency filter for the American mobile telephone system. 806-815 - H. Jonathan Chao, Necdet Uzun:
An ATM routing and concentration chip for a scalable multicast ATM switch. 816-828 - Alberto Bilotti, Gerardo Monreal, Ravi Vig:
Monolithic magnetic Hall sensor using dynamic quadrature offset cancellation. 829-836 - Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi:
SRAM bitline circuits on PD SOI: advantages and concerns. 837-844 - Toru Tanzawa, Tomoharu Tanaka:
A stable programming pulse generator for single power supply flash memories. 845-851 - Chi-Chang Wang, Jiin-Chuan Wu:
Efficiency improvement in charge pump circuits. 852-860 - Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada:
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. 861-869 - John A. McNeill:
Jitter in ring oscillators. 870-879 - Heung-Joon Park, Mani Soma:
Analytical model for switching transitions of submicron CMOS logics. 880-889 - Stephen I. Long, Johnny Qi Zhang:
Low power GaAs current-mode 1.2 Gb/s interchip interconnections. 890-897 - Xiaoyun Hu, Kenneth W. Martin:
A switched-current sample-and-hold circuit. 898-904 - Ion E. Opris, Gregory T. A. Kovacs:
A high-speed median circuit. 905-908 - Jae-Tack Yoo, Kent F. Smith, Ganesh Gopalakrishnan:
A fast parallel squarer based on divide-and-conquer. 909-912 - Chiu-Sing Choy, M. H. Ku, Chi Fat Chan:
A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions. 913-917 - P. J. Wright, R. U. Madurawe:
An SRAM cell with nonvolatile memory for programmable logic applications. 918-919 - Ozan Ersan Erdogan:
Comments on "A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter". 920
Volume 32, Number 7, July 1997
- Luca Schillaci, Andrea Baschirotto, Rinaldo Castello:
A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz. 926-932 - Olivier Nys, Robert K. Henderson:
A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging. 933-942 - Vincenzo Peluso, Michiel S. J. Steyaert, Willy Sansen:
A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique. 943-952 - Nicolas Moeneclaey, Andreas Kaiser:
Design techniques for high-resolution current-mode sigma-delta modulators. 953-958 - Damien McCartney, Adrian Sherry, John O'Dowd, Pat Hickey:
A low-noise low-drift transducer ADC. 959-967 - Christian Menolfi, Qiuting Huang:
A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors. 968-976 - Wim Dehaene, Michiel S. J. Steyaert, Willy Sansen:
A 50-MHz standard CMOS pulse equalizer for hard disk read channels. 977-988 - Clemens H. J. Mensink, Bram Nauta, Hans Wallinga:
A CMOS "soft-switched" transconductor and its application in gain control and filters. 989-998 - Daniel Aebischer, Henri J. Oguey, Vincent von Kaenel:
A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA. 999-1005 - Denis Flandre, Albert Viviani, Jean-Paul Eggermont, Bernard Gentinne, Paul G. A. Jespers:
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. 1006-1012 - Rafael Domínguez-Castro, Servando Espejo, Ángel Rodríguez-Vázquez, Ricardo Carmona, Péter Földesy, Ákos Zarándy, Péter Szolgay, Tamás Szirányi, Tamás Roska:
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage. 1013-1026 - Yang Ni, Francis Devos, Mohammed Boujrad, Jianhong Guan:
Histogram-equalization-based adaptive image sensor for real-time vision. 1027-1036 - Wang Ping, José E. Franca:
A CMOS 1.0-μm two-dimensional analog multirate system for real-time image processing. 1037-1048 - Andreas Wild, John Quigley, James Feddeler, Steven Ledford, James Caravella, Fred Shapiro, Ben Gilsdorf, Merit Hong, Dave Mietus, Robert B. Davies, Rajiv Parmar, Jy-Der Tai, Jim Thomas, June Quarberg, Eytan Hartung, Tony Sawan, Jim H. Carlquist, Ken Papworth, Juan Buxo, Mike Schriber, Michael Berens, Drew Warren, Brynette Smith, Michael Mazuelos, Kim Bass, Larry Layton:
A 0.9-V microcontroller for portable applications. 1049-1055 - Michael Dolle, Satwinder Jhand, Walter Lehner, Otto Müller, Manfred Schlett:
A 32-b RISC/DSP microprocessor with reduced complexity. 1056-1066 - Christian Piguet, Jean-Marc Masgonty, Claude Arm, Serge Durand, Thierry Schneider, Flavio Rampogna, Ciro Scarnera, Christian Iseli, Jean-Paul Bardyn, R. Pache, Evert Dijkstra:
Low-power design of 8-b embedded CoolRisc microcontroller cores. 1067-1078 - Reto Zimmermann, Wolfgang Fichtner:
Low-power logic styles: CMOS versus pass-transistor logic. 1079-1090 - Tim Cummins, Brian Murray, Colm Prendergast:
A PAL/NTSC digital video encoder on 0.6-μm CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2° differential phase. 1091-1100 - Kazuya Yamanaka, Sumitaka Takeuchi, Shuji Murakami, Masayuki Koyama, Jun Ido, Takashi Fujiwara, Susumu Hirano, Keisuke Okada, Tadashi Sumi:
A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode. 1101-1107 - Daniel Weil, Alain Botta, Alain Chemarin, Philippe Gallay, Jacques Majos, Michel Servel:
A 16×622 Mb/s ATM switch: PRELUDE switch architecture integrated into a 6-million transistor monochip. 1108-1114 - Andrew Le Fevre, Robin Flet:
A 100 Mb/s multi-LAN crosspoint chip set for cable management. 1115-1121 - F. Balestro, V. Fraisse, Gilbert Martel, Dominique Morche, Patrice Senn, G. Le Tourneur, Yannick Mahieux:
A 3-V 0.5-μm CMOS A/D audio processor for a microphone array. 1122-1126 - Andrea Baschirotto, Guido Brasca, Federico Montecchi, Fabrizio Stefani:
A low-power BiCMOS switched-capacitor filter for audio codec applications. 1127-1131 - Henri J. Oguey, Daniel Aebischer:
CMOS current reference without resistance. 1132-1135 - Mark Ingels, Michiel S. J. Steyaert:
Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's. 1136-1141 - Robert Rogenmoser, Hubert Kaeslin:
The impact of transistor sizing on power efficiency in submicron CMOS circuits. 1142-1145 - Jan Mulder, Albert C. van der Woerd, Wouter A. Serdijn, Arthur H. M. van Roermund:
An RMS-DC converter based on the dynamic translinear principle. 1146-1150 - P. J. Sulivan, B. A. Xavier, Walter H. Ku:
Low voltage performance of a microwave CMOS Gilbert cell mixer. 1151-1155 - M. Rau, T. Oberst, R. Lares, Albrecht Rothermel, R. Schweer, N. Menoux:
Clock/data recovery PLL using half-frequency clock. 1156-1159
Volume 32, Number 8, August 1997
- Keng Leong Fong, Christopher Dennis Hull, Robert G. Meyer:
A class AB monolithic mixer for 900-MHz applications. 1166-1172 - Fan You, Sherif H. K. Embabi, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio:
Am improved tail current source for low voltage applications. 1173-1180 - Johan Wulleman:
A low-power high-gain transresistance BiCMOS pulse amplifier for capacitive detector readout. 1181-1191 - Chih-Cheng Hsieh, Chung-Yu Wu, Tai-Ping Sun:
A new cryogenic CMOS readout structure for infrared focal plane array. 1192-1199 - John Lazzaro, John Wawrzynek, Richard P. Lippmann:
A micropower analog circuit implementation of hidden Markov model state decoding. 1200-1209 - Ricardo Gonzalez, Benjamin M. Gordon, Mark A. Horowitz:
Supply and threshold voltage scaling for low power CMOS. 1210-1216 - Nobuaki Otsuka, Mark A. Horowitz:
Circuit techniques for 1.5-V power supply flash memory. 1217-1230 - Toru Tanzawa, Tomoharu Tanaka:
A dynamic analysis of the Dickson charge pump circuit. 1231-1240 - Pong-Fei Lu, Ching-Te Chuang, Jin Ji, Lawrence F. Wagner, Chang-Ming Hsieh, Jente B. Kuang, Louis Lu-Chen Hsu, Mario M. Pelella Jr., Shao-Fu Sanford Chu, Carl J. Anderson:
Floating-body effects in partially depleted SOI CMOS circuits. 1241-1253 - Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni:
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. 1254-1262 - Kerry S. Lowe:
A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch. 1263-1268 - Chuc K. Thanh, Stephen H. Lewis, Paul J. Hurst:
A second-order double-sampled delta-sigma modulator using individual-level averaging. 1269-1273 - Robert Wodnicki, Gordon W. Roberts, Martin D. Levine:
A log-polar image sensor fabricated in a standard 1.2-μm ASIC CMOS process. 1274-1277 - Gert Cauwenberghs, Volnei A. Pedroni:
A low-power CMOS analog vector quantizer. 1278-1283 - Paul M. Furth, Andreas G. Andreou:
On fault probabilities and yield models for VLSI neural networks. 1284-1287 - Robert L. Franch, J. Ji, C. L. Chen:
A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file. 1288-1292 - Ming-Dou Ker:
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current. 1293-1296 - José Francisco López, Kamran Eshraghian, Roberto Sarmiento, Antonio Núñez, Derek Abbott:
GaAs pseudodynamic latched logic for high performance processor cores. 1297-1303
Volume 32, Number 9, September 1997
- Wayne Struble, Finbarr McGrath, Kevin Harrington, Pierce Nagle:
Understanding linearity in wireless communication amplifiers. 1310-1318 - James F. Imbornone, Michael T. Murphy, Robert S. Donahue, Eugene Heaney:
New insight into subharmonic oscillation mode of GaAs power amplifiers under severe output mismatch condition. 1319-1325 - O. S. Andy Tang, K. H. George Duh, S. M. Joseph Liu, Phillip M. Smith, William F. Kopp, Thomas J. Rogers, David J. Pritchard:
Design of high-power, high-efficiency 60-GHz MMICs using an improved nonlinear PHEMT model. 1326-1333 - Tsuneo Tokumitsu, Makoto Hirano, Kimiyoshi Yamasaki, Chikara Yamaguchi, Kenjiro Nishikawa, Masayoshi Aikawa:
Highly integrated three-dimensional MMIC technology applied to novel masterslice GaAs- and Si-MMICs. 1334-1341 - Jan-Erik Müller, Thomas Grave, Heinz J. Siweris, Martin Kärner, Andre Schäfer, Harald Tischer, Henning Riechert, Lothar Schleicher, Ludger Verweyen, Axel Bangert, Walter Kellner, Thomas Meier:
A GaAs HEMT MMIC chip set for automotive radar systems fabricated by optical stepper lithography. 1342-1349 - Sal Nati, Ian Kyles:
A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution. 1350-1356 - Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano:
A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs. 1357-1362 - Taiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda:
40-Gb/s ICs for future lightwave communications systems. 1363-1370 - Mehran Mokhtari, Thomas Swahn, Robert H. Walden, William E. Stanchina, Michael Kardos, Tarja Juhola, Gerd Schuppener, Hannu Tenhunen, Thomas Lewin:
InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V. 1371-1383 - Manfred Lang, Zhi-Gong Wang, Zhihao Lao, Michael Schlechtweg, Andreas Thiede, Michaela Rieger-Motzer, Martin Sedler, Wolfgang Bronner, Gudrun Kaufel, Klaus Köhler, Axel Hülsmann, Brian Raynor:
20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver. 1384-1393 - Stefan van Waasen, Andreas Umbach, Uwe Auer, Heinz-Gunter Bach, Ralf Michael Bertenburg, Guido Janssen, Gebre Giorgis Mekonnen, Wolfgang Passenberg, Ralf Reuter, Wolfgang Schlaak, Carsten Schramm, Günter Unterbörsch, Peter Wolfram, Franz-Josef Tegude:
27-GHz bandwidth high-speed monolithic integrated optoelectronic photoreceiver consisting of a waveguide fed photodiode and an InAlAs/InGaAs-HFET traveling wave amplifier. 1394-1401 - Fuminobu Ono, Zenzo Singu, Kazunori Asano, Junko Morikawa, Masaaki Kuzuhara, Fumiaki Emori:
A 50-W low distortion GaAs MESFET for digital cellular base stations. 1402-1404 - J. Mondal, K. Peterson, K. Wong, K. Vu, S. Consolazio, S. Geske, J. Blubaugh, W. Guthrie, G. Dietz, R. Haubenstricker, H. Fudem, S. Moghe:
A highly integrated multifunction macro synthesizer chip (MMSC) for applications in 2-18 GHz synthesized sources. 1405-1409 - Barrie Gilbert:
The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage. 1412-1423 - Shoji Otaka, Hiroshi Tanimoto, Shuji Watanabe, Tadahiko Maeda:
A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter. 1424-1429 - Sorin P. Voinigescu, Michael C. Maliepaard, Jonathan L. Showell, Greg E. Babcock, David Marchesan, Michael Schroter, Peter Schvan, David L. Harame:
A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. 1430-1439 - Joachim N. Burghartz, Mehmet Soyuer, Keith A. Jenkins, Michael Kies, Margaret Dolan, Kenneth J. Stein, John Malinowski, David L. Harame:
Integrated RF components in a SiGe bipolar technology. 1440-1445 - Farbod Behbahani, Ali Fotowat, Saeed Navid, Rainer Gaethke, Micheal Delurio:
A low distortion bipolar mixer for low voltage direct up-conversion and high IF systems. 1446-1450 - Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, David L. Harame:
An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator. 1451-1454 - Robert A. Groves, David L. Harame, Dale Jadus:
Temperature dependence of Q and inductance in spiral inductors fabricated in a silicon-germanium/BiCMOS technology. 1455-1459 - Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, Ryuushi Shimokawa:
Error suppressing encode logic of FCDL in a 6-b flash A/D converter. 1460-1464 - Bruce J. Tesch, Juan C. Garcia:
A low glitch 14-b 100-MHz D/A converter. 1465-1469 - Jim Bales:
A low-power, high-speed, current-feedback op-amp with a novel Class AB high current output stage. 1470-1474 - Bernhard Zojer, Rüdiger Koban, Reinhard Petschacher, Wolfgang Sereinig:
A 150-V subscriber line interface circuit (SLIC) in a new BiCMOS/DMOS-technology. 1475-1480
Volume 32, Number 10, October 1997
- Changhyun Kim, Kensall D. Wise:
Low-voltage electronics for the stimulation of biological neural networks using fully complementary BiCMOS circuits. 1483-1490 - Angelo Nagari, Andrea Baschirotto, Federico Montecchi, Rinaldo Castello:
A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter. 1491-1498 - Jen-Shi Wu, Ming-Luen Liou, Hsi-Pin Ma, Tzi-Dar Chiueh:
A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]. 1499-1510 - Manop Thamsirianunt, Tadeusz Kwasniewski:
CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications. 1511-1524 - Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik:
Flexible test mode approach for 256-Mb DRAM. 1525-1534 - Ho-Jun Song:
A self-off-time detector for reducing standby current of DRAM. 1535-1542 - Jaume Segura, Antonio Rubio:
A detailed analysis of CMOS SRAM's with gate oxide short defects. 1543-1550 - Kerry S. Lowe:
Bufferless broadcasting: a low power distributed circuit technique for broadcasting 10-Gb/s chip input signals. 1551-1555 - Zhihao Lao, Wolfgang Bronner, Andreas Thiede, Michael Schlechtweg, Axel Hülsmann, Michaela Rieger-Motzer, Gudrun Kaufel, Brian Raynor, Martin Sedler:
35-GHz static and 48-GHz dynamic frequency divider ICs using 0.2-μm AlGaAs/GaAs-HEMTs. 1556-1562 - Giuseppe Ferri, Willy Sansen:
A rail-to-rail constant-gm low-voltage CMOS operational transconductance amplifier. 1563-1567 - Massimo Franciotta, G. Colli, Rinaldo Castello:
A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier. 1568-1572 - Peter J. Langlois:
Compensation in variable ratio current mirrors. 1573-1575 - M. van de Gevel, J. C. Kuenen, Jan Davidse, Arthur H. M. van Roermund:
Low-power MOS integrated filter with transconductors with spoilt current sources. 1576-1581 - Yuichi Kado, T. Ohno, Mitsuru Harada, K. Deguchi, T. Tsuchiya:
An ultralow power CMOS/SIMOX programmable counter LSI. 1582-1587 - Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III:
A CMOS high-speed data recovery circuit using the matched delay sampling technique. 1588-1596 - Hoi-Jun Yoo:
A study of pipeline architectures for high-speed synchronous DRAMs. 1597-1603 - Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya:
A 0.5-V MTCMOS/SIMOX logic gate. 1604-1609 - Gerard M. Blair:
Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings". 1610-1611
Volume 32, Number 11, November 1997
- David A. Carlson, Ruben W. Castelino, Robert O. Mueller:
Multimedia extensions for a 550-MHz RISC microprocessor. 1618-1624 - Cliff A. Maier, James A. Markevitch, Cheryl Senter Brashears, Tim Sippel, Earl T. Cohen, Jim Blomgren, James G. Ballard, Jay Pattin, Viki Moldenhauer, Jeffrey A. Thomas, George Taylor:
A 533-MHz BiCMOS superscalar RISC microprocessor. 1625-1634 - Gianfranco Gerosa, Mike Alexander, Jose Alvarez, Cody Croxton, Michael D'Addeo, A. Richard Kennedy, Carmine Nicoletta, James P. Nissen, Ross Philip, Paul Reed, Hector Sanchez, Scott A. Taylor, Brad Burgess:
A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. 1635-1649 - Don Draper, Matt Crowley, John Holst, Greg Favor, Albrecht Schoy, Jeff Trull, Amos Ben-Meir, Rajesh Khanna, Dennis Wendell, Ravi Krishna, Joe Nolan, Dhiraj Mallick, Hamid Partovi, Mark Roberts, Mark Johnson, Thomas H. Lee:
Circuit techniques in a 266-MHz MMX-enabled processor. 1650-1664 - Charles F. Webb, Carl J. Anderson, Leon J. Sigal, Kenneth L. Shepard, John S. Liptay, James D. Warnock, Brian W. Curran, Barry Krumm, Mark D. Mayo, Peter J. Camporese, Eric M. Schwarz, Mark S. Farrell, Phillip J. Restle, Robert M. Averill III, Timothy J. Slegel, William V. Huott, Yuen H. Chan, Bruce Wile, Thao N. Nguyen, Philip G. Emma, Daniel K. Beece, Ching-Te Chuang, Cyril Price:
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. 1676-1682 - Stefanos Sidiropoulos, Mark A. Horowitz:
A semidigital dual delay-locked loop. 1683-1692 - William C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson:
A low-power microprocessor based on resonant energy. 1693-1701 - David L. Harris, Mark A. Horowitz:
Skew-tolerant domino circuits. 1702-1711 - Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma:
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. 1712-1720 - Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto:
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. 1721-1727 - Atsushi Hatakeyama, Hirohiko Mochizuki, Tadao Aikawa, Masato Takita, Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi, Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Toru Anezaki, Masatomo Hasegawa, Masao Taguchi:
A 256-Mb SDRAM using a register-controlled digital DLL. 1728-1734 - Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi:
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM. 1735-1742 - Takashi Okuda, Tatsunori Murotani:
A four-level storage 4-Gb DRAM. 1743-1747 - Tae-Sung Jung, Do-Chan Choi, Sung-Hee Cho, Myong-Jae Kim, Seung-Keun Lee, Byung-Soon Choi, Jin-Sun Yum, San-Hong Kim, Dong-Gi Lee, Jong-Chang Son, Myung-Sik Yong, Heung-Kwun Oh, Sung-Bu Jun, Woung-Moo Lee, E. Haq, Kang-Deog Suh, S. B. Ali, Hyung-Kyu Lim:
A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology. 1748-1757 - Kazuyuki Nakamura, Koichi Takeda, Hideo Toyoshima, Kenji Noda, Hiroaki Ohkubo, Tetsuya Uchida, Toshiyuki Shimizu, Toshiro Itani, Ken Tokashiki, Koji Kishimoto:
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. 1758-1765 - Wai Lee, Paul E. Landman, Brock Barton, Shigeshi Abiko, Hiroshi Takahashi, Hiroyuki Mizuno, Shigetoshi Muramatsu, Kenichi Tashiro, Masahiro Fusumada, Luat Pham, Frederic Boutaud, Emmanuel Ego, Girolamo Gallo, Hiep Tran, Carl Lemonds, Albert Shih, Mahalingam Nandakumar, Robert H. Eklund, Ih-Chin Chen:
A 1-V programmable DSP for wireless communications [CMOS]. 1766-1776 - Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill:
A low-power 128-tap digital adaptive equalizer for broadband modems. 1777-1789 - Harry Neuteboom, Ben M. J. Kup, Mark Janssens:
A DSP-based hearing instrument IC. 1790-1806 - Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina:
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. 1807-1816 - Albert van der Werf, Fons Brüls, Richard P. Kleihorst, Erwin Waterlander, Math J. W. Verstraelen, Thomas Friedrich:
I.McIC: a single-chip MPEG-2 video encoder for storage. 1817-1823 - Roberto Alini, Giorgio Betti, Ivan Bietti, Giacomino Bollati, Francesco Brianti, Angelo Dati, Marco Demicheli, Paolo Gadducci, Stefano Marchese, Emanuele Marconetti, Valerio Pisati, Maurizio Zuffada, Rinaldo Castello, Fereidoon Heydari, Peter Gillen, Gerry Maguire, Marcus Marrow, Stephen McDonagh, Fergus O'Brien, Jerry O'Brien, Niall O'hEarcain, Deirdre Reddy, Lisa Fredrickson, Dennis Stone, LeRoy Volz:
A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo. 1824-1838 - Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj:
A 160-MHz analog equalizer for magnetic disk read Channel. 1858-1865 - Sung-Ung Kwak, Bang-Sup Song, Kantilal Bacrania:
A 15-b, 5-Msample/s low-spurious CMOS ADC. 1866-1875 - Pieter Vorenkamp, Raf Roovers:
A 12-b, 60-MSample/s cascaded folding and interpolating ADC. 1876-1886 - Klaas Bult, Aaron Buchwald:
An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2. 1887-1895 - Todd L. Brooks, David H. Robertson, Daniel F. Kelly, Anthony Del Muro, Stephen W. Harston:
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR. 1896-1906 - Daniel Senderowicz, Germano Nicollini, Sergio Pernici, Angelo Nagari, Pierangelo Confalonieri, Carlo Dallavalle:
Low-voltage double-sampled ΣΔ converters. 1907-1919 - Adrian K. Ong, Bruce A. Wooley:
A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz. 1920-1934 - Stephen A. Jantzi, Kenneth W. Martin, Adel S. Sedra:
Quadrature bandpass ΔΣ modulation for digital radio. 1935-1950 - Thorsten Baumheinrich, Bernd Prégardier, Ulrich Langmann:
A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC. 1951-1960 - Andrew N. Karanicolas:
A 2.7-V 300-MS/s track-and-hold amplifier. 1961-1967 - Manfred Punzenberger, Christian C. Enz:
A 1.2-V low-power BiCMOS class AB log-domain filter. 1968-1978 - Andrea Baschirotto, Rinaldo Castello:
A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing. 1979-1986 - Francesco Rezzi, Ivan Bietti, Marco Cazzaniga, Rinaldo Castello:
A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization. 1987-1999 - Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio:
Multistage amplifier topologies with nested Gm-C compensation. 2000-2011 - Richard Griffith, Robert L. Vyne, Robert N. Dotson, Tom Petty:
A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion mode input stage. 2012-2022 - Stewart S. Taylor:
A GaAs MESFET Schottky diode barrier height reference circuit. 2023-2029 - Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Keijiro Umehara, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa:
A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras. 2030-2041 - Yoshinori Iida, Eiji Oba, Keiji Mabuchi, Nobuo Nakamura, Hiroki Miura:
A 1/4-inch 330 K square pixel progressive scan CMOS active pixel image sensor. 2042-2047 - Michael H. Perrott, Theodore L. Tewksbury III, Charles G. Sodini:
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation. 2048-2060 - Arvin Shahani, Derek K. Shaeffer, Thomas H. Lee:
A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver. 2061-2070 - Jacques C. Rudell, Jia-Jiunn Ou, Thomas Byunghak Cho, George Chien, Francesco Brianti, Jeffrey A. Weldon, Paul R. Gray:
A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications. 2071-2088 - Taizo Yamawaki, Masaru Kokubo, Kiyoshi Irie, Hiroaki Matsui, Kazuaki Hori, Takefumi Endou, Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Makoto Katagishi, Julian Robert Hildersley:
A 2.7-V GSM RF transceiver IC. 2089-2096 - Robert G. Meyer, William D. Mack, Johannes J. E. M. Hageraats:
A 2.5-GHz BiCMOS transceiver for wireless LAN's. 2097-2104 - Pieter J. G. van Lieshout, Rudy J. van de Plassche:
A power-efficient, low-distortion variable gain amplifier consisting of coupled differential pairs. 2105-2110
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