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"A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller."

Gianfranco Gerosa et al. (1997)

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DOI: 10.1109/4.641684

access: closed

type: Journal Article

metadata version: 2022-07-07

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  - journals/jssc/GerosaAACDKNNPR97
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  - https://dblp.org/rec/journals/jssc/GerosaAACDKNNPR97
Gianfranco Gerosa, Mike Alexander, Jose Alvarez, Cody Croxton, Michael D'Addeo, A. Richard Kennedy, Carmine Nicoletta, James P. Nissen, Ross Philip, Paul Reed, Hector Sanchez, Scott A. Taylor, Brad Burgess:
A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. IEEE J. Solid State Circuits 32(11): 1635-1649 (1997)

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