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Hiroshi Inokawa
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2020 – today
- 2024
- [j13]Somrita Ghosh
, Aritra Acharyya, Arindam Biswas, Amit Banerjee
, Hiroshi Inokawa, Hiroaki Satoh, Alexey Y. Seteikin, I. G. Samusev:
Multiple Quantum Barrier Avalanche Photodiode Based on GaN/AlGaN Heterostructures for Long Wavelength Infrared Detection. IEEE Access 12: 16022-16038 (2024) - 2023
- [j12]Arie Pangesti Aji, Hiroaki Satoh, Catur Apriono
, Eko Tjipto Rahardjo
, Hiroshi Inokawa
:
Folded-Dipole Antenna Geometrical Analysis for THz Microbolometer. IEEE Access 11: 25713-25722 (2023) - [j11]Hiroaki Satoh
, Koki Isogai, Shohei Iwata, Taiki Aso, Ryosuke Hayashi, Shu Takeuchi, Hiroshi Inokawa
:
Refractive Index Measurement Using SOI Photodiode with SP Antenna toward SOI CMOS-Compatible Integrated Optical Biosensor. Sensors 23(2): 568 (2023) - 2022
- [j10]Hiroaki Satoh
, Ken Kawakubo, Atsushi Ono, Hiroshi Inokawa:
Angle-sensitive pixel based on silicon-on-insulator p-n junction photodiode with aluminum grating gate electrode. IEICE Electron. Express 19(21): 20220428 (2022) - [j9]Arie Pangesti Aji, Hiroaki Satoh
, Catur Apriono
, Eko Tjipto Rahardjo, Hiroshi Inokawa
:
Responsivity and NEP Improvement of Terahertz Microbolometer by High-Impedance Antenna. Sensors 22(14): 5107 (2022) - 2020
- [j8]Anitharaj Nagarajan
, Shusuke Hara, Hiroaki Satoh
, Aruna Priya Panchanathan, Hiroshi Inokawa:
Angular selectivity of SOI photodiode with surface plasmon antenna. IEICE Electron. Express 17(13): 20200187 (2020) - [j7]Anitharaj Nagarajan
, Shusuke Hara, Hiroaki Satoh
, Aruna Priya Panchanathan
, Hiroshi Inokawa
:
Angle-Sensitive Detector Based on Silicon-On-Insulator Photodiode Stacked with Surface Plasmon Antenna. Sensors 20(19): 5543 (2020)
2010 – 2019
- 2018
- [j6]Yash Sharma, Hiroaki Satoh, Hiroshi Inokawa
:
Application of bow-tie surface plasmon antenna to silicon on insulator nanowire photodiode for enhanced light absorption. IEICE Electron. Express 15(11): 20180328 (2018) - 2016
- [c6]Hiroshi Inokawa, Norihiro Katayama, Mitsuyuki Nakao
:
Evaluation of multidrug cancer chronotherapy based on cell cycle model under influences of circadian clock. EMBC 2016: 1439-1442 - 2012
- [j5]Mingu Jo, Yuki Kato, Masashi Arita
, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa
, Yasuo Takahashi, Jung-Bum Choi:
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. IEICE Trans. Electron. 95-C(5): 865-870 (2012)
2000 – 2009
- 2009
- [j4]Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa
, Yasuo Takahashi:
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. Int. J. Nanotechnol. Mol. Comput. 1(2): 58-69 (2009) - 2007
- [j3]Wancheng Zhang, Katsuhiko Nishiguchi
, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi
, Hiroshi Inokawa
, Yasuo Takahashi, Nan-Jian Wu:
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. IEICE Trans. Electron. 90-C(5): 943-948 (2007) - [j2]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13(3): 249-266 (2007) - 2006
- [c5]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa
, Katsuhiko Nishiguchi, Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2006: 19 - 2005
- [c4]Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2005: 32-38 - 2004
- [c3]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL 2004: 262-268 - [c2]Hiroshi Inokawa
, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274 - 2003
- [c1]Hiroshi Inokawa
, Yasuo Takahashi:
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ISMVL 2003: 259-266
1990 – 1999
- 1997
- [j1]Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa
, Toshiaki Tsuchiya:
A 0.5-V MTCMOS/SIMOX logic gate. IEEE J. Solid State Circuits 32(10): 1604-1609 (1997)
Coauthor Index
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