12. VLSI Design 1999: Goa, India

Invited Talks

• Robert A. Pease: Invited Talk: The Information Appliance and Its Interface to the Analog World: Easy - Or Not So Easy.

TCAD to ECAD I

• Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell: Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis. 6-11
• Li-Fu Chang, Abhay Dubey, Keh-Jeng Chang, Robert Mathews, Ken Wong: Incorporating Process Induced Effects into RC Extraction. 12-17
• Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas:
  A New Methodology for Concurrent Technology Development and Cell Library Optimization. 18-25
  

Low Power I

• Bedabrata Pain, Guang Yang, Brita Olson, Timothy Shaw, Monico Ortiz, Julie Heynssens, Chris Wrigley, Charlie Ho:
  A Low-Power Digital Camera-on-a-Chip Implemented in CMOS Active Pixel Approach. 26-31
  
• Anantha Chandrakasan, Abram P. Dancy, James Goodman, Thomas Simon: A Low-Power Wireless Camera System. 32-36
• Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva:
  Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. 37-41
  
• Mahesh Mehendale, Sunil D. Sherlekar: Low Power Code Generation of Multiplication-free Linear Transforms. 42-47
• Nithya Raghavan, Venkatesh Akella, Smita Bakshi:
  Automatic Insertion of Gated Clocks at Register Transfer Level. 48-54
  
• Kavita Nair, Ramesh Harjani:
  Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. 55-60
  
• P. K. Singh, Sriram Jayasimha: A Low-Complexity, Reduced-Power Viterbi Algorithm. 61-66
• Basabi Bhaumik, Pravas Pradhan, G. S. Visweswaran, Rajamohan Varambally, Anand Hardi: A Low Power 256 KB SRAM Design. 67-71

Testing I

• Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita: Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. 72-77
• R. D. (Shawn) Blanton:
  IDDQ-Testability of Tree Circuits. 78-86
  
• M. Jamoussi: Test-Vector Prediction of M-Testable Iterative Arrays. 87-90
• C. P. Ravikumar, Manish Sharma, R. K. Patney: Improving the Diagnosability of Digital Circuits. 629-634
• Sujit T. Zachariah, Sreejit Chakravarty: A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. 91-94
• C. P. Ravikumar, Ajay Mittal:
  Hierarchical Delay Fault Simulation. 635-
  
• Basabi Bhaumik, G. S. Visweswaran, R. Lakshminarasimhan: A New Test Compression Scheme. 95-99
• Vinod K. Agarwal: Invited Talk: Embedded Test for Systems-on-a-Chip.

TCAD to ECAD II

• Andrew B. Kahng: Mini-Tutorial: IC Layout and Manufacturability: Critical Links and Design Flow Implications. 100-105
• Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky: New and Exact Filling Algorithms for Layout Density Control. 106-110
• Fang-Cheng Chang, Melissa Kwok, Kenneth Rachlin, Robert Pack: Silicon-Level Physical Verification of Sub Wavelength(tm) Designs. 603-
• Franklin M. Schellenberg: Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops. 111-119
• Akis Doganis, James C. Chen: Interconnect Simple, Accurate and Statistical Models Using On-Chip Measurements for Calibration. 120-127

Co-Design and Synthesis

• Rashmi Goswami, V. Srinivasan, M. Balakrishnan:
  MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. 128-132
  
• V. Rajesh, Rajat Moona: Processor Modeling for Hardware Software Codesign. 132-137
• Mattias O'Nils, Axel Jantsch:
  Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols. 138-145
  
• Apostolos A. Kountouris, Christophe Wolinski:
  Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification. 146-150
  
• Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa:
  Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. 151-156
  
• Manpreet S. Khaira: nvited Talk: Micro-2010: Lead Microprocessor for 2010 - Myth or Reality? 157-159

Analog Design I

• Satrajit Gupta, Lalit M. Patnaik:
  Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms. 160-163
  
• A. B. Bhattacharyya, Saudas Dey: Sub-Circuit Analysis for Power Supply Rejection Ratio in Regulated Cascode Operational Transconductance Amplifiers and Filters. 164-168
• Shabbir H. Batterywala, H. Narayanan: Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. 169-174
• Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury:
  A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. 175-180
  
• Robert Thacker, Wendy Belluomini, Chris J. Myers:
  Timed Circuit Synthesis Using Implicit Methods. 181-188
  
• Pradip Mandal, V. Visvanathan: A New Approach for CMOS Op-Amp Synthesis. 189-195

Multi-Valued Logic

• Robert K. Brayton, Sunil P. Khatri: Multi-Valued Logic Synthesis. 196-105
• Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Sequential Multi-Valued Network Simplification using Redundancy Removal. 206-211
  
• Shugang Wei, Kensuke Shimizu: Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits. 212-217
• Luca Macchiarulo, Pierluigi Civera: Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. 218-

Verification I

• Partha Pratim Chakrabarti, Pallab Dasgupta, Partha Pratim Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose:
  Controlling State Explosion in Static Simulation by Selective Composition. 226-231
  
• Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham: FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. 232-235
• Peter M. Maurer:
  Efficient Simulation for Hierarchical and Partitioned Circuits. 236-241
  
• Ajoy C. Siddabathuni, M. Balakrishnan: Simulation and Modeling of a Multicast ATM Switch. 242-
• Ramayya Kumar: Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go?

Testing II

• Irith Pomeranz, Sudhakar M. Reddy:
  VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. 250-255
  
• Pradip A. Thaker, Mona E. Zaghloul, Minesh B. Amin:
  Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. 256-259
  
• Zbigniew Kalbarczyk, Janak H. Patel, Myeong S. Lee, Ravishankar K. Iyer: An Approach to Evaluating the Effects of Realistic Faults in Digital Circuits. 260-265
• Debaleena Das, Nur A. Touba:
  A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems. 266-269
  
• Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner: Design and Test of MEMs. 270-

Verification II

• Vishnu A. Patankar, Alok Jain, Randal E. Bryant:
  Formal Verification of an ARM Processor. 282-287
  
• Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John:
  Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. 288-293
  
• Jatindra Kumar Deka, Pallab Dasgupta, P. P. Chakrabarti:
  An Efficiently Checkable Subset of TCTL for Formal Verification of Transition Systems with Delays. 294-299
  
• Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen:
  Superscalar Processor Validation at the Microarchitecture Level. 300-305
  
• Tamarah Arons, Amir Pnueli:
  Verifying Tomasulo's Algoithm by Refinement. 306-309
  
• Jeremy Casas, Hannah Honghua Yang, Manpreet Khaira, Mandar Joshi, Thomas Tetzlaff, Steve W. Otto, Erik Seligman:
  Logic Verification of Very Large Circuits Using Shark. 310-317
  
• Ingo Sander, Axel Jantsch: Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. 318-323
• Pankaj Chauhan, Pallab Dasgupta, P. P. Chakrabarti:
  Exploiting Isomorphism for Compaction and Faster Simulation of Binary Decision Diagrams. 324-
  

DSP

• Anupam Basu, Rainer Leupers, Peter Marwedel: Array Index Allocation under Register Constraints in DSP Programs. 330-335
• D. V. R. Murthy, S. Ramachandran, S. Srinivasan:
  Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. 336-339
  
• Bupesh Pandita, Subir K. Roy:
  Design and Implementation of Viterbi Decoder Using FPGAs. 611-
  
• M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale:
  Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. 340-345
  
• Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar:
  A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. 346-349
  
• S. Ramanathan, V. Visvanathan, S. K. Nandy:
  Synthesis of Configurable Architectures for DSP Algorithms. 350-357
  
• Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag:
  Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. 358-
  

Logic Synthesis

• Peichen Pan, Guohua Chen:
  Optimal Retiming for Initial State Computation. 366-371
  
• Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns: Performance Driven Synthesis for Pass-Transistor Logic. 372-377
• B. N. V. Malleswara Gupta, H. Narayanan, Madhav P. Desai:
  A State Assignment Scheme Targeting Performance and Area. 378-383
  
• S. Ramesh:
  Efficient Translation of Statecharts to Hardware Circuits. 384-389
  
• Chitrasena Bhat, Niranjan N. Chiplunkar:
  Heuristic Technology Mapper For Lut Based Fpgas. 390-393
  
• Rajeev Murgai, Jawahar Jain, Masahiro Fujita:
  Efficient Scheduling Techniques for ROBDD Construction. 394-401
  
• Prashant Saxena, Peichen Pan, C. L. Liu:
  The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. 402-407
  
• Amit Narayon:
  Recent Advances in BDD Based Representations for Boolean Functions: A Survey. 408-
  

Low Power II

• Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik: POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. 416-422
• Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh:
  Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. 423-427
  
• Mircea R. Stan:
  Optimal Voltages and Sizing for Low Power. 428-433
  
• Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss:
  Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. 434-439
  
• Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy: Characterizing Individual Gate Power Sensitivity in Low Power Design. 625-
• Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan:
  Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. 440-
  

Physical Design I

• Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal:
  GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. 448-452
  
• Avaneendra Gupta, John P. Hayes:
  Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. 453-459
  
• C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram:
  COST Circuit Optimization SysTem in ASIC Library Development Environment. 460-463
  
• Andrew B. Kahng, Sudhakar Muddu, Egino Sarto: Interconnect Optimization Strategies for High-Performance VLSI Designs. 464-469
• Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang:
  Modeling Crosstalk in Resistive VLSI Interconnections. 470-475
  
• Noel Menezes, Chung-Ping Chen:
  Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. 476-
  

Testing III

• Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal:
  A Test Generator for Segment Delay Faults. 484-491
  
• Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell:
  A Complete Characterization of Path Delay Faults through Stuck-at Faults. 492-497
  
• Jue Wu, Elizabeth M. Rudnick:
  A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. 498-505
  
• Shashank K. Mehta, Sharad C. Seth:
  Empirical Computation of Reject Ratio in VLSI Testing. 506-511
  
• Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya:
  Synthesis of Symmetric Functions for Path-Delay Fault Testability. 512-517
  
• Sudip Chakrabarti, Abhijit Chatterjee:
  Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models. 518-523
  

Digital Design and Applications

• Rajiv V. Joshi, Wei Hwang:
  Design Considerations and Implementation of a High Performance Dynamic Register File. 526-531
  
• Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri: A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata. 532-537
• Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili:
  Lossy Compression of Images Using Logic Minimization. 538-543
  
• Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee:
  Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. 544-547
  
• Lov K. Grover: Invited Talk: Quantum Computation. 548-

Physical Design II

• Sree Ganesan, Ranga Vemuri: FAAR: A Router for Field-Programmable Analog Arrays. 556-563
• Sandip Das, Subhas C. Nandy, Bhargab B. Bhattacharya:
  High Performance MCM Routing: A New Approach. 564-569
  
• Jayadeva:
  Sequential Chaotic Annealing and its Application to Multilayer Channel Routing. 570-573
  
• Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
  Satisfiability-Based Detailed FPGA Routing. 574-577
  
• Pradip K. Kar, Subir K. Roy:
  TECHMIG: A Layout Tool for Technology Migration. 615-620
  
• Andrew B. Kahng, Sudhakar Muddu:
  Improved Effective Capacitance Computations for Use in Logic and Layout Optimization. 578-583
  

Analog Design II

• Onuttom Narayan, Jaijeet S. Roychowdhury:
  Analyzing Forced Oscillators with Multiple Time Scales. 621-
  
• Joonbae Park, Yido Koo, Wonchan Kim:
  A Semi-Digital Delay Locked Loop for Clock Skew Minimization. 584-588
  
• Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. 589-596
• Pramodchandran N. Variyam, Junwei Hou, Abhijit Chatterjee:
  Test Generation for Analog Circuits Using Partial Numerical Simulation. 597-602
  

Tutorials

• Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno: CAD Techniques for Embedded System Design. 608
• Manuel d'Arbreu, Abhijit Chatterjee: Manufacturability of Mixed Signal Systems. 608
• Kaushik Roy, Anand Raghunathan, Sujit Dey: Low Power Design Methodologies for Systems-on-Chips. 609
• Rahul Razdan, Apurva Kalia, Manu Lauria: Verification of Systems-on-Chip Designs. 609
• Sudip Nag, H. K. Verma, Kaushik Roy: VLSI Signal Processing in FPGAs. 609
• Janusz Rajski, Jerzy Tyszer, Sanjay Patel: Built-In Self-Test for Systems on Silicon. 609-610

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