ITC 2007: Santa Clara, California, USA

Microprocessor Test

• Robert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem:
  On-chip timing uncertainty measurements on IBM microprocessors. 1-7
  
• Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh:
  Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. 1-8
  
• Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick:
  Test cost reduction for the AMD™ Athlon processor using test partitioning. 1-10
  

Improving Test Quality

• Kunal P. Ganeshpure, Sandip Kundu:
  On ATPG for multiple aggressor crosstalk faults in presence of gate delays. 1-7
  
• Ritesh P. Turakhia, W. Robert Daasch, Mark Ward, John Van Slyke:
  Silicon evaluation of longest path avoidance testing for small delay defects. 1-10
  
• Jennifer Dworak:
  Which defects are most critical? optimizing test sets to minimize failures due to test escapes. 1-10
  

Memory Testing

• Kevin Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin:
  Advancements in at-speed array BIST: multiple improvements. 1-10
  
• Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga:
  A concurrent approach for testing address decoder faults in eFlash memories. 1-10
  
• Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao:
  Diagnosis for MRAM write disturbance fault. 1-9
  

New Serdes Test Techniques

• Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma:
  Data jitter measurement using a delta-time-to-voltage converter method. 1-7
  
• Mike P. Li, Jinhua Chen:
  New methods for receiver internal jitter measurement. 1-10
  
• Stephen K. Sunter, Aubin Roy:
  A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes. 1-8
  

SOC Test

• Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty:
  Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs. 1-9
  
• Zhiyuan He, Zebo Peng, Petru Eles:
  A heuristic for thermal-safe SoC test scheduling. 1-10
  
• Érika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski:
  Redefining and testing interconnect faults in Mesh NoCs. 1-10
  

Getting Accustomed to Unknowns

• Peter Wohl, John A. Waicukauski, Sanjay Ramnath:
  Fully X-tolerant combinational scan compression. 1-10
  
• Nur A. Touba:
  X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR. 1-10
  
• Andreas Leininger, Martin Fischer, Michael Richter, Michael Gössel:
  Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques. 1-9
  

Advanced Diagnosis Algorithms

• Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Will Hsu, Yuan-Shih Chen, Albert Mann:
  Diagnose compound scan chain and system logic defects. 1-10
  
• Ruifeng Guo, Yu Huang, Wu-Tung Cheng:
  A complete test set to diagnose scan chain failures. 1-10
  
• Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang:
  Interconnect open defect diagnosis with minimal physical information. 1-10
  

Breaking the 10-GB/s Barrier

• David C. Keezer, Dany Minier, Patrice Ducharme, Doris Viens, Greg Flynn, John McKillop:
  Multi-GHz loopback testing using MEMs switches and SiGe logic. 1-10
  
• Jose Moreira, Heidi Barnes, Guenter Hoersch:
  Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications. 1-10
  
• Minh Quach, Mark Hinton, Regee Petaja:
  Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applications. 1-9
  

Microprocessor Test Advances

• Samy Makar, Tony Altinis, Niteen Patkar, Janet Wu:
  Testing of Vega2, a chip multi-processor with spare processors. 1-10
  
• Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li:
  The design-for-testability features of a general purpose microprocessor. 1-9
  
• Frank Frederick, Teresa L. McLaurin:
  Design for test features of the ARM clock control macro. 1-8
  

Advances in ATPG and Delay Test

• Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir:
  Analyzing the risk of timing modeling based on path delay tests. 1-10
  
• Ankur Parikh, Weixin Wu, Michael S. Hsiao:
  Mining-guided state justification with partitioned navigation tracks. 1-10
  
• Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou:
  An efficient SAT-based path delay fault ATPG with an unified sensitization model. 1-7
  

Advanced Characterization Methods

• Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy:
  Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. 1-10
  
• Zahi S. Abuhamdeh, Vincent D'Alassandro, Richard Pico, Dale Montrone, Alfred L. Crouch, Andrew Tracy:
  Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip. 1-10
  
• Yukio Okuda:
  Gate delay ratio model for unified path delay analysis. 1-10
  

HF in Volume Production

• Udaya Shankar Natarajan, Hemalatha Shanmugasundaram, Prachi Deshpande, Chin Soon Wah:
  Rapid UHF RFID silicon debug and production testing. 1-10
  
• Yongquan Fan, Yi Cai, Zeljko Zilic:
  A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. 1-10
  
• Brian Moore, Chris Sellathamby, Philippe Cauvet, Hérvé Fleury, M. Paulson, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky:
  High throughput non-contact SiP testing. 1-10
  

Power-aware Testing

• V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
  A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. 1-10
  
• Bin Li, Lei Fang, Michael S. Hsiao:
  Efficient power droop aware delay fault testing. 1-10
  
• V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
  PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. 1-9
  

New Advances in Detecting PCBA Structural Defects

• Mike Farrell, Glen Leinbach:
  Implementing bead probe technology for in-circuit test: A case study. 1-8
  
• Kenneth P. Parker, Don DeMille:
  A bead probe CAD strategy for in-circuit test. 1-8
  
• Tee Chwee Liong, Andy Pascual:
  Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI). 1-10
  

Towards More Efficient Defect Diagnosis

• Osei Poku, Ronald D. Blanton:
  Delay defect diagnosis using segment network faults. 1-10
  
• Dongok Kim, Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau:
  Testing for systematic defects based on DFM guidelines. 1-10
  
• Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann:
  Faster defect localization in nanometer technology based on defective cell diagnosis. 1-10
  

New Tests for PLLs

• Hideo Okawara:
  Real-time signal processing - a new PLL test approach. 1-9
  
• Guo Yu, Peng Li:
  A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures. 1-10
  
• Takahiro J. Yamaguchi, H. X. Hou, Koji Takayama, Dave Armstrong, Masahiro Ishida, Mani Soma:
  An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time. 1-8
  

Delay Test Topics

• Gefu Xu, Adit D. Singh:
  Achieving high transition delay fault coverage with partial DTSFF scan chains. 1-9
  
• Rohit Kapur, Jindrich Zejda, Thomas W. Williams:
  Fundamentals of timing information for test: How simple can we get? 1-7
  
• Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise:
  Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation. 1-10
  

Test and Debug Data Reduction

• Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef:
  Programmable deterministic Built-In Self-Test. 1-9
  
• Seongmoon Wang, Zhanglei Wang, Wenlong Wei, Srimat T. Chakradhar:
  A low cost test data compression technique for high n-detection fault coverage. 1-10
  
• Ehab Anis, Nicola Nicolici:
  On using lossless compression of debug data in embedded logic analysis. 1-10
  

Functional and Outlier Test

• Tao Xu, Krishnendu Chakrabarty:
  Functional testing of digital microfluidic biochips. 1-10
  
• Onur Guzey, Li-C. Wang, Jayanta Bhadra:
  Enhancing signal controllability in functional test-benches through automatic constraint extraction. 1-10
  
• Jeffrey L. Roehr:
  Measurement ratio testing for improved quality and outlier detection. 1-10
  

Testing the Future - ATE to the Rescue!

• Andrew C. Evans:
  The new ATE: Protocol aware. 1-10
  
• Seong-Hun Choe, Shuji Tanaka, Masayoshi Esashi:
  A matched expansion MEMS probe card with low CTE LTCC substrate. 1-6
  
• William J. Bowhers:
  Management of common-mode currents in semiconductor ATE. 1-9
  

Advances in DFT

• Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal:
  SPARTAN: a spectral and information theoretic approach to partial-scan. 1-10
  
• Dean L. Lewis, Hsien-Hsin S. Lee:
  A scanisland based design enabling prebond testability in die-stacked microprocessors. 1-8
  
• Jing Li, Swaroop Ghosh, Kaushik Roy:
  A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. 1-10
  

Advanced Concepts in Board and System Test

• Carl Edward Gray, Odile Liboiron-Ladouceur, David C. Keezer, Keren Bergman:
  Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network. 1-9
  
• Kenneth P. Parker, Stephen Hird:
  Finding power/ground defects on connectors - a new approach. 1-7
  
• Heiko Ehrenberg:
  IEEE P1581 can solve your board level memory cluster test problems. 1-9
  

Characterization with Delay Test, I_DDQ and Probing

• Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir:
  Statistical analysis and optimization of parametric delay test. 1-10
  
• Rudolf Schlangen, Reiner Leihkauf, Uwe Kerst, Christian Boit, Rajesh Jain, Tahir Malik, Keneth R. Wilsher, Ted Lundquist, Bernd Krüger:
  Backside E-Beam Probing on Nano scale devices. 1-9
  
• Michael Laisne, Triphuong Nguyen, Song-lin Zuo, Xiangdong Pan, Hailong Cui, Cher Bai, A. Street, M. Parley, Neetu Agrawal, K. Sundararaman:
  Verification and debugging of IDDQ test of low power chips. 1-7
  

DFT and Analog Testing

• Srividya Sundar, Bruce C. Kim, Toby Byrd, Felipe Toledo, Sudhir Wokhlu, Erika Beskar, Raul Rousselin, David Cotton, Gary Kendall:
  Low cost automatic mixed-signal board test using IEEE 1149.4. 1-9
  
• Fang Liu, Sule Ozev:
  Efficient simulation of parametric faults for multi-stage analog circuits. 1-9
  
• Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Egas Henes Neto, Gilson I. Wirth, Luigi Carro:
  Using built-in sensors to cope with long duration transient faults in future technologies. 1-10
  

Reducing Test Power

• Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
  A novel scheme to reduce power supply noise for high-quality at-speed scan testing. 1-10
  
• Qiang Xu, Dianwei Hu, Dong Xiang:
  Pattern-directed circuit virtual partitioning for test power reduction. 1-10
  
• Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
  California scan architecture for high quality and low power testing. 1-10
  

Fault Simulation

• Soumitra Bose, Vishwani D. Agrawal:
  Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. 1-10
  
• Dong Xiang, Yang Zhao, Kaiwei Li, Hideo Fujiwara:
  Fast and effective fault simulation for path delay faults based on selected testable paths. 1-10
  
• Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal:
  Delay fault simulation with bounded gate delay mode. 1-10
  

Fault and Error Tolerance in Nanotechnologies

• Shideh Shahidi, Sandeep K. Gupta:
  ERTG: A test generator for error-rate testing. 1-10
  
• Ramtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham:
  ACCE: Automatic correction of control-flow errors. 1-10
  
• Xiaojun Ma, Jing Huang, Fabrizio Lombardi:
  Modeling facet roughening errors in self-assembly by snake tile sets. 1-10
  

RF Test Methods

• Erkan Acar, Sule Ozev:
  Low cost characterization of RF transceivers through IQ data analysis. 1-10
  
• Koji Asami:
  An algorithm to evaluate wide-band quadrature mixers. 1-7
  
• Fang Liu, Erkan Acar, Sule Ozev:
  Test yield estimation for analog/RF circuits over multiple correlated measurements. 1-10
  

Defect Tolerance in Microprocessors

• Yukiya Miura:
  Dependable clock distribution for crosstalk aware design. 1-9
  
• Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
  Novel compensation scheme for local clocks of high performance microprocessors. 1-9
  
• Miltiadis Hatzimihail, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis:
  A methodology for detecting performance faults in microprocessors via performance monitoring hardware. 1-10
  

The Last Word on N-Detect Test!

• Irith Pomeranz, Sudhakar M. Reddy:
  On the saturation of n-detection test sets with increased n. 1-10
  
• Gaurav Bhargava, Dale Meehl, James Sage:
  Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns. 1-7
  
• Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke:
  Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. 1-10
  

System Issues with Test

• Jukka Antila, Timo Karhu:
  A comparative study of continuous sampling plans for functional board testing. 1-7
  
• Teresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim:
  Enhanced testing of clock faults. 1-9
  
• Alex S. Biewenga, Frans de Jong:
  SiP-test: Predicting delivery quality. 1-10
  

ADC Test

• Luís Rolíndez, Salvador Mir, Jean-Louis Carbonéro, Dimitri Goguet, Nabil Chouba:
  A stereo audio Σ∑ ADC architecture with embedded SNDR self-test. 1-10
  
• Hochul Kim, Kye-shin Lee:
  Sigma-delta ADC characterization using noise transfer function pole-zero tracking. 1-9
  
• Hanqing Xing, Hanjun Jiang, Degang Chen, Randall L. Geiger:
  A fully digital-compatible BIST strategy for ADC linearity testing. 1-10
  

IJTAG and SJTAG Boundary-Scan-Based System Test

• Alfred L. Crouch:
  IJTAG: The path to organized instrument connectivity. 1-10
  
• Bradford G. Van Treuren, Adam W. Ley:
  JTAG system test in a MicroTCA world. 1-10
  
• Gunnar Carlsson, Johan Holmqvist, Erik Larsson:
  Protocol requirements in an SJTAG/IJTAG environment. 1-9
  

Power Issues in Test

• Swarup Bhunia, Kaushik Roy:
  Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. 1-10
  
• Srivaths Ravi:
  Power-aware test: Challenges and solutions. 1-10
  
• Sachin Idgunji:
  Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges. 1-10
  

System Test Strategies

• Parmod Aggarwal:
  Cost effective manufacturing test using mission mode tests. 1-8
  
• Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren:
  A practical approach to comprehensive system test & debug using boundary scan based test architecture. 1-10
  

Reliability and Test

• Ming Zhang:
  Design-for-reliability: A soft error case study. 1
  
• Subhasish Mitra, Mridul Agarwal:
  Circuit failure prediction to overcome scaled CMOS reliability challenges. 1-3
  
• Michael Nicolaidis:
  GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies. 1-10
  

Panels

• Steve Comen:
  Where is car IC testing going? 1
  
• Bernd Gessner:
  How to ensure zero defects from the beginning with semiconductor test methods. 1-2
  
• Gary Wittie:
  Car IC test changing but the same quality goal. 1
  
• Davide Appello:
  Automotive IC's: less testing, more prevention. 1-2
  
• Peter M. O'Neill:
  Statistical test: A new paradigm to improve test effectiveness & efficiency. 1-10
  
• Andrew Marshall:
  A universal DC to logic performance correlation. 1-4
  
• Peter Maxwell:
  Principles and results of some test cost reduction methods for ASICs. 1-5
  

Last update Fri May 25 08:24:30 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page