ICCAD 1990:
Santa Clara, California, USASession 1A:
Routing Algorithms and Complexity 1
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Session 1B:
Timing Analysis and Verification
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conf/iccad/GrodsteinPGGY90 export record as
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Session 1C:
Verification
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Eduard Cerny ,
C. Mauras :
Tautology Checking Using Cross-Controllability and Cross-Observability Relations.
34-37
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Session 2A:
Routing Methods
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conf/iccad/PrasitjutrakulK90 export record as
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conf/iccad/KawamuraSSMO90
Session 2B:
Performance Enhancements for Logic and Switch-Level Simulation
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Peter M. Maurer :
Optimization of the Parallel Technique for Compiled Unit-Delay Simulation.
70-73
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Session 2C:
Interacting Sequential Machines and Boolean Function Manipulation
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Wayne Wolf :
An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine Networks.
80-83
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conf/iccad/SrinivasanKMB90
Session 3A:
Floorplanning Algorithms
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Session 3B:
Yield Maximization
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M. A. Styblinski :
Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi Approach.
112-115
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Session 3C:
Sequential Verification
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Session 4A:
Floorplanning Systems
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Alexander Herrigel :
GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design.
152-155
Session 4B:
Circuit Simulation
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conf/iccad/VisweswariahFR90 export record as
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Rui Wang ,
Omar Wing :
Analysis of VLSI Microconductor Systems by Bi-Level Waveform Relaxation.
166-169
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Session 4C:
Logic Synthesis
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conf/iccad/VanbekbergenCGM90 export record as
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Session 5A:
Analog Layout
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conf/iccad/ShiraishiKKHSK90 export record as
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Session 5B:
High-Level Synthesis
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conf/iccad/RundensteinerGB90 export record as
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Rajiv Jain :
MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations.
212-215
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Session 5C:
Automatic Test Pattern Generation
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conf/iccad/MahlstedtGOD90 export record as
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Session 6A:
Layout Desgin and Verification
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Hirotoshi Sawada :
A Hierarchical Circuit Extractor Based on New Cell Overlap Analysis.
240-243
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Session 6B:
Scheduling and Allocation
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Session 6C:
Topics in Testing
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Susana Stoica :
A Hierarchical Approach for Testing Large Circuits.
268-271
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Session 7A:
Analog Design and Test
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conf/iccad/HocevarADDSK90 export record as
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Session 7B:
Datapath Synthesis
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David Knapp :
Feedback-Driven Datapath Optimization in Fasolt.
300-303
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Session 7C:
Partial Scan and Test Minimization
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Session 8A:
Placement
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Session 8B:
Design Management in CAD Frameworks
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conf/iccad/BretschneiderKLHW90 export record as
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Session 8C:
Built-In Self Test and Diagnostics
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Session 9A:
Technology Driven Routing
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Session 9B:
Reliability Simulation
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Ulrich Jagau :
SIMCURRENT: An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits.
396-399
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Session 9C:
Sequential Optimization
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Session 10A:
Routing Algorithms and Complexity 2
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Masato Edahiro :
A Clock Net Reassignment Algorithm Usign Voronoi Diagram.
420-423
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Session 10B:
Parallel Matrix Techniques
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conf/iccad/MayaramYCBAC90 export record as
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Session 10C:
Synthesis for Test and Diagnosis
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Session 11A:
Exploratory Initiatives in CAD Frameworks
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Session 11B:
Switch and Logic Simulation
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Session 11C:
Combinatorial Optimization
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conf/iccad/VasudevamurthyR90
Session 12A:
Partitioning and Module Generation
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Session 12B:
Linear Circuit Simulation
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Session 12C:
Synthesis Systems
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