A. Richard Newton (Ed.):
Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991.
ACM 1991, ISBN 0-89791395-7
28. DAC 1991:
San Francisco, California, USA
Application of Mixed Integer Linear Programming to High-Level Synthesis
Louis J. Hafer
: Constraint improvements for MILP-based hardware synthesis.
Circuit and Timing Simulation
: Global Stratgies for Electronic Design (Panel Abstract).
Multi-Layer Area Routing
Synthesis and Delay Testing
Design Automation in the Soviet Union
: Implementing the Vision: Electronic Design in the 1990's (Panel Abstract).
Over the Cell Channel Routing
Leading-Edge Design Systems
Improving Simulator Performance
Synthesis for Programmable Gate Arrays
: Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays.
: Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays.
Nam Sung Woo
: A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility.
: What is Design for Manufacturability (DFM)? (Panel Abstract).
Design for Testability and Built In Self Test
Synthesis of Asynchronous Circuits
A. Richard Newton
: Framework Standards: How Important are They? (Panel Abstract).
Global Considerations in Routing
Test Pattern Generation
Datapath and Control Synthesis
Formal Design Verification
Partitioning and Placement
: Are Formal Methods in Design for Real? (Panel Abstract).
CAD for Analog Cells and ICs
Interfacing to High-Level Synthesis:
Above and Below
Thomas E. Fuhrman
: Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World.
Critical Path Analysis of Logic Gate Networks
Timing Modeling of Interconnect
Synthesis of High-Performance Systems
Placement for Performance Optimization
Wing K. Luk
: A Fast Physical Constraint Generator for Timing Driven Layout.
: An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs.
Extending the Functionality of Discrete Simulation
Farid N. Najm
: Transition Density, A Stochastic Measure of Activity in Digital Circuits.
Scheduling in High-Level Synthesis I
Jerry P. Hwang
: REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis.
Matthias C. Utesch
: A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions.
Transmission Line and Interconnect Simulation
Scheduling in High-Level Synthesis II
: Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract).