28. DAC 1991:
San Francisco, California, USA A. Richard Newton (Ed.):
Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991.
ACM 1991, ISBN 0-89791395-7 Application of Mixed Integer Linear Programming to High-Level Synthesis
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Louis J. Hafer :
Constraint improvements for MILP-based hardware synthesis.
14-19
Circuit and Timing Simulation
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Panel
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Harvey Jones :
Global Stratgies for Electronic Design (Panel Abstract).
38
Multi-Layer Area Routing
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Deborah C. Wang :
Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing.
49-53
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Synthesis and Delay Testing
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Technology Mapping
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conf/dac/YoshikawaITSNK91
Design Automation in the Soviet Union
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Panel
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Andrew Rappaport :
Implementing the Vision: Electronic Design in the 1990's (Panel Abstract).
119
Over the Cell Channel Routing
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Fault Simulation
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Yoshihiro Kitamura :
Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT.
151-154
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Sequential Synthesis
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Panel
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Leading-Edge Design Systems
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Dwight D. Hill :
A CAD System for the Design of Field Programmable Gate Arrays.
187-192
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Improving Simulator Performance
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Larry G. Jones :
Accelerating Switch-Level Simulation by Function Caching.
211-214
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Synthesis for Programmable Gate Arrays
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Kevin Karplus :
Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays.
240-243
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Kevin Karplus :
Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays.
244-247
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Nam Sung Woo :
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility.
248-251
Panel
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Wojciech Maly :
What is Design for Manufacturability (DFM)? (Panel Abstract).
252
Layout Systems
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Design for Testability and Built In Self Test
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conf/dac/ChakrabortyBBL91 export record as
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Chien-In Henry Chen :
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit.
287-290
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Synthesis of Asynchronous Circuits
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Panel
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A. Richard Newton :
Framework Standards: How Important are They? (Panel Abstract).
315
Global Considerations in Routing
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Test Pattern Generation
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Stephen Pateras ,
Janusz Rajski :
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits.
347-352
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Datapath and Control Synthesis
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conf/dac/PapachristouCH91 export record as
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Formal Design Verification
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Partitioning and Placement
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Testability Analysis
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Logic Optimization
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Panel
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Gerd Venzl :
Are Formal Methods in Design for Real? (Panel Abstract).
474
Module Generators
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CAD for Analog Cells and ICs
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Interfacing to High-Level Synthesis:
Above and Below
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Thomas E. Fuhrman :
Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World.
520-525
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Critical Path Analysis of Logic Gate Networks
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Timing Modeling of Interconnect
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Technology CAD
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Synthesis of High-Performance Systems
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Panel
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conf/dac/Sangiovanni-Vincentelli91
Placement for Performance Optimization
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Wing K. Luk :
A Fast Physical Constraint Generator for Timing Driven Layout.
626-631
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conf/dac/SutanthavibulS91 export record as
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Arvind Srinivasan :
An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs.
636-639
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Extending the Functionality of Discrete Simulation
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Farid N. Najm :
Transition Density, A Stochastic Measure of Activity in Digital Circuits.
644-649
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Scheduling in High-Level Synthesis I
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Frameworks
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Geometric Algorithms
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Jerry P. Hwang :
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis.
717-722
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Matthias C. Utesch :
A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions.
723-726
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Transmission Line and Interconnect Simulation
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Scheduling in High-Level Synthesis II
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Panel
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Jonathan Rose :
Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract).
779
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