27. DAC 1990: Orlando, Florida, USA

HDL Validation and Intermediate Format

Probabilistic Techniques in Placement: Annealing and Its Competitors

Binary Decision Diagrams - Implementations and Applications

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New Scheduling, Allocation and Mapping Techniques

Timing Driven Layout Techniques

Timing Verification

Data Management and Version Control

Data Path Optimization Algorithms

Issues in Floorplanning

Formal Methods for Design Verification

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Synthesis and Testability

Tutorial: Layout Synthesis of MOS Digital Cells

Layout Verification

Software Engineering in Design Automation

Boolean Methods

Layout Synthesis: Cell Assembly

Computer Aids For IC Manufacturability

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Timing and Routing Optimization in Synthesis

Compactors: Theory and Practice

Electrical Simulation

Object-Oriented Approaches

Scheduling Algorithms for High-Level Synthesis

Layout Synthesis: Leaf Cell Generation

Accelerating Logic Simulation

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Data Path Synthesis

Tutorial: Symbolic Simulation - Techniques and Applications

Testing Systems

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Applications of Behavioral Synthesis

Performance Constrained Routing

Testing Using Functional Models

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Decomposition and Partitioning in Logic Synthesis

New Approaches to Routing Problems

Combinational Test Generation

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Alternative Approaches to Behavioral Synthesis

Channel-Oriented Multilayer Routing

Ideas in Testing