27. DAC 1990: Orlando, Florida, USA

HDL Validation and Intermediate Format

Probabilistic Techniques in Placement: Annealing and Its Competitors

Binary Decision Diagrams - Implementations and Applications


New Scheduling, Allocation and Mapping Techniques

Timing Driven Layout Techniques

Timing Verification

Data Management and Version Control

Data Path Optimization Algorithms

Issues in Floorplanning

Formal Methods for Design Verification


Synthesis and Testability

Tutorial: Layout Synthesis of MOS Digital Cells

Layout Verification

Software Engineering in Design Automation

Boolean Methods

Layout Synthesis: Cell Assembly

Computer Aids For IC Manufacturability


Timing and Routing Optimization in Synthesis

Compactors: Theory and Practice

Electrical Simulation

Object-Oriented Approaches

Scheduling Algorithms for High-Level Synthesis

Layout Synthesis: Leaf Cell Generation

Accelerating Logic Simulation


Data Path Synthesis

Tutorial: Symbolic Simulation - Techniques and Applications

Testing Systems


Applications of Behavioral Synthesis

Performance Constrained Routing

Testing Using Functional Models


Decomposition and Partitioning in Logic Synthesis

New Approaches to Routing Problems

Combinational Test Generation


Alternative Approaches to Behavioral Synthesis

Channel-Oriented Multilayer Routing

Ideas in Testing

maintained by Schloss Dagstuhl LZI at University of Trier