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"An Adaptive Timing-Driven Layout for High Speed VLSI."

Suphachai Sutanthavibul, Eugene Shragowitz (1990)

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DOI: 10.1145/123186.123233

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/SutanthavibulS90
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  - https://dblp.org/rec/conf/dac/SutanthavibulS90
Suphachai Sutanthavibul, Eugene Shragowitz:
An Adaptive Timing-Driven Layout for High Speed VLSI. DAC 1990: 90-95

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