26. DAC 1989:
Las Vegas, Nevada, USA Donald E. Thomas (Ed.):
Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989.
ACM Press 1989
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David Marple :
Transistor Size Optimization in the Tailor Layout System.
43-48
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Osamu Karatsu :
VLSI Design Language Standardization Effort in Japan.
50-55
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S. Hayati ,
A. Parker :
Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions.
75-80
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Larry Soulé ,
Anoop Gupta :
Characterization of Parallelism and Deadlocks in Distributed Digital Logic Simulation.
81-86
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M. J. Chung ,
Y. Chung :
Data Parallel Simulation Using Time-Warp on the Connection Machine.
98-103
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Michael C. McFarland :
The Social Implications of Computerization: Making the Technology Humane.
129-134
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P. Groenveld :
On Global Wire Ordering for Macro-Cell Routing.
155-160
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K. A. Tamura :
Locating Functional Errors in Logic Circuits.
185-191
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Alan J. Coppola :
New Methods in the Analysis of Logic Minimization Data and Algorithms.
226-231
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Chi-Yuan Lo :
Automatic Tub Region Generation for Symbolic Layout Compaction.
302-306
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Kurt Keutzer :
Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation.
308-313
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Srinivas Devadas :
General Decomposition of Sequential Machines: Relationships to State Assignment.
314-320
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Pierre G. Paulin :
Horizontal Partitioning of PLA-based Finite State Machines.
333-338
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conf/dac/PrasitjutrakulK89 export record as
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Sarma Sastry ,
Jen-I Pi :
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems.
382-387
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conf/dac/Libeskind-HadasL89 export record as
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M. L. Yu :
A Study of the Applicability of Hopfield Decision Neural Nets to VLSI CAD.
412-417
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K. Cho ,
Randal E. Bryant :
Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation.
418-423
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F. E. Norrod :
An Automatic Test Generation Algorithm for Hardware Description Languages.
429-434
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conf/dac/Muller-GlaserB89 export record as
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conf/dac/DragomireckyGJDSd89 export record as
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David Knapp :
An Interactive Tool for Register-level Structure Optimization.
598-601
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Nam Sung Woo ,
H. Shin :
A Technology-adaptive Allocation of Functional Units and Connections.
602-605
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Andrew T. Yang ,
S. M. Kang :
iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development.
630-633
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A. K. George :
Evaluating Hardware Models in DIGITAL's System Simulation Environment.
642-644
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Kuang-Wei Chiang :
Resistance Extraction and Resistance Calculation in GOALIE?
682-685
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T. Ghewala :
CrossCheck: A Cell Based VLSI Testability Solution.
706-709
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Steven S. Leung :
Behavioral Modeling of Transmission Gates in VHDL.
746-749
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J. Blanks :
Partitioning by Probability Condensation.
758-761
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S. Chowdhury :
Optimum Design of Reliable IC Power Networks Having General Graph Topologies.
787-790
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conf/dac/PitaksanonkulTLG89 export record as
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W. Li ,
H. Switzer :
A Unified Data Exchange Environment Based on EDIF.
803-806
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conf/dac/KollaritschLMSS89 export record as
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M. Roberts :
CEDIF: A Data Driven EDIF Reader.
818-821
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L. G. Jones :
Fast Online/Offline Netlist Compilation of Hierarchical Schematics.
822-825
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