Cover

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  Title Page.
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  Copyright.

Introduction

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  Foreword.
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  ATS Steering Committee.
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  Advisory Board and Organizing Committee.
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  Program Committee.
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  Reviewers.
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  Best Paper Awards (2002 and 2003).
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  TTTC Introduction.
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  TTEP Introduction.

Tutorials

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  Yervant Zorian, Juan Antonio Carballo: T1: Design for Manufacturability.
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  Adit D. Singh: T2: Statistical Methods for VLSI Test and Burn-in Optimization.

Plenary Talk

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  Thomas W. Williams: Design for Testability: The Path to Deep Submicron.

Banquet Speeches

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  Sanjiv Taneja: DFT Aware Layout - Layout Aware DFT.
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  Janusz Rajski: Embedded Test Technology - Brief History, Current Status, and Future Directions.

Invited Talks

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  John P. Hayes: Faults and Tests in Quantum Circuits.
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  Sreejit Chakravarty: Improving Logic Test Quality of Microprocessors.

Session A1: Analog and RF Testing: I

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  Donghoon Han, Abhijit Chatterjee: Robust Built-In Test of RF ICs Using Envelope Detectors. 2-7
• 
  Haihua Yan, Adit D. Singh, Gefu Xu: Delay Defect Characterization Using Low Voltage Test. 8-13
• 
  Shalabh Goyal, Michael Purtell: Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester. 14-17
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  Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka: IDDQ Testing Method using a Scan Pattern for Production Testing. 18-21
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  Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel: A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. 22-27

Session B1: Verification, On-line and Software Testing

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  Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee: An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. 28-33
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  Amir Hekmatpour, Azadeh Salehi: Block-based Schema-driven Assertion Generation for Functional Verification. 34-39
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  K. Uday Bhaskar, M. Prasanth, V. Kamakoti, Kailasnath Maneparambil: A Framework for Automatic Assembly Program Generator (A²PG) for Verification and Testing of Processor Cores. 40-45
• 
  Guangmei Zhang, Chen Rui, Xiaowei Li, Han Congying: The Automatic Generation of Basis Set of Path for Path Testing. 46-51

Session A2: Analog and RF Testing: II

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  Yongsheng Wang, Jinxiang Wang, Fengchang Lai, Yizheng Ye: Optimal Schemes for ADC BIST Based on Histogram. 52-57
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  A. M. Majid, David C. Keezer, J. V. Karia: A 5 Gbps Wafer-Level Tester. 58-63
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  Achintya Halder, Abhijit Chatterjee: Low-cost Production Test of BER for Wireless Receivers. 64-69
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  Shaolei Quan, Qiang Qiang, Chin-Long Wey: Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. 70-75

Session B2: Self-Checking, On-line and Software Testing

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  Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel: New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. 76-81
• 
  Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong: A State Machine for Detecting C/C++ Memory Faults. 82-87
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  Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar: On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. 88-93
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  Philip Samuel, Rajib Mall: Boundary Value Testing based on UML Models. 94-99

Session A3: Interconnect Testing

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  Jiun-Lang Huang: Random Jitter Testing Using Low Tap-Count Delay Lines. 100-105
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  Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu: Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. 106-111
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  Wichian Sirisaengtaksin, Sandeep K. Gupta: A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. 112-119
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  Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li: Non-robust Test Generation for Crosstalk-Induced Delay Faults. 120-125

Session B3: BIST

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  Dong Xiang, Ming-Jing Chen, Hideo Fujiwara: Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. 126-131
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  Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz: Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. 132-137
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  Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed: Low Transition LFSR for BIST-Based Applications. 138-143
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  Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang: A BIST Scheme Based on Selecting State Generation of Folding Counters. 144-149

Session A4: SoC Testing

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  Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara: Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. 150-155
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  Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi: Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. 156-161
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  Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng: SOC Test Scheduling with Test Set Sharing and Broadcasting. 162-169

Session B4: Yield Enhancement

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  Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. 170-175
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  Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. 176-181
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  Yu-Chun Dawn, Jen-Chieh Yeh, Cheng-Wen Wu, Chia-Ching Wang, Yung-Chen Lin, Chao-Hsun Chen: Flash Memory Die Sort by a Sample Classification Method. 182-187
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  Junichi Hirase, Tatsuya Furukawa: Chip Identification using the Characteristic Dispersion of Transistor. 188-193

Session A5: Delay and Defect-Based Testing

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  Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty: Untestable Multi-Cycle Path Delay Faults in Industrial Designs. 194-201
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  Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz: Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. 202-207
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  I-De Huang, Sandeep K. Gupta: Selection of Paths for Delay Testing. 208-215
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  Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy: On Improving Defect Coverage of Stuck-at Fault Tests. 216-223

Session B5: Low Power Testing

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  Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: A Scan Matrix Design for Low Power Scan-Based Test. 224-229
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  Youbean Kim, Myung-Hoon Yang, Yong Lee, Sungho Kang: A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. 230-235
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  Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi: ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing. 236-241
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  Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: Partial Gating Optimization for Power Reduction During Test Application. 242-247

Session A6: Diagnosis, Delay, and Defect-Based Testing

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  Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy: Bridge Defect Diagnosis with Physical Information. 248-253
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  Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara: Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. 254-259
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  Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja: A Class of Linear Space Compactors for Enhanced Diagnostic. 260-265
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  Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. 266-271

Session B6: Test Generation and Fault Simulation

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  Dong Hyun Baik, Kewal K. Saluja: State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. 272-277
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  Shahrzad Mirkhani, Zainalabedin Navabi: Enhancing Fault Simulation Performance by Dynamic Fault Clustering. 278-283
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  Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar: Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. 284-287
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  Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara: An Effective Design for Hierarchical Test Generation Based on Strong Testability. 288-293
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  Vishwani D. Agrawal, Alok S. Doshi: Concurrent Test Generation. 294-299

Session A7: Design for Testability

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  V. R. Devanathan: Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. 300-305
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  Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara: A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. 306-311
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  Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press: Achieving High Test Quality with Reduced Pin Count Testing. 312-317
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  Dong Xiang, Kaiwei Li, Hideo Fujiwara: Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. 318-323

Session B7: Test Compression and Compaction

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  Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. 324-329
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  Sameer Goel, Rubin A. Parekhji: Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. 330-336
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  Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: Efficient Test Compaction for Pseudo-Random Testing. 337-342
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  Yu-Hsuan Fu, Sying-Jyan Wang: Test Data Compression with Partial LFSR-Reseeding. 343-347

Session A8: Design for Testability: II

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  Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya: CryptoScan: A Secured Scan Chain Architecture. 348-353
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  Shiyi Xu: Pseudo-Parity Testing with Testable Design. 354-359
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  Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen: Finite State Machine Synthesis for At-Speed Oscillation Testability. 360-365
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  Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa: A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. 366-371

Session B8: Test Compression, Test Compaction, and Defect-Based Testing

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  Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra: Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. 372-377
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  Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait: Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. 378-385
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  Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura: Low Power Test Compression Technique for Designs with Multiple Scan Chain. 386-389
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  Zhigang Jiang, Sandeep K. Gupta: Threshold testing: Covering bridging and other realistic faults. 390-397

Session A9: Design for Testability: III

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  Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das: Synthesis of Testable Finite State Machine Through Decomposition. 398-403
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  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. 404-409
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  Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay: Flip-flop chaining architecture for power-efficient scan during test application. 410-413
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  Varun Arora, Indranil Sengupta: A Unified Approach to Partial Scan Design using Genetic Algorithm. 414-421

Session B9: Fault Modeling, Processor Testing, and Memory Testing

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  Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes: A Family of Logical Fault Models for Reversible Circuits. 422-427
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  Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil: Compressing Functional Tests for Microprocessors. 428-433
• 
  Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. 434-439
• 
  Ji-Xue Xiao, Guang-Ju Chen, Yong-Le Xie: Arithmetic Test Strategy for FFT Processor. 440-443
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  Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki: Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. 444-449

Industry Session

Session C1: SoC Test Practices

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  Tom Waayers, Erik Jan Marinissen, Maurice Lousberg: IEEE Std 1500 Compliant Infrastructure forModular SOC Testing. 450
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  Rubin A. Parekhji: DFT for Low Cost SOC Test. 451
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  R. Chandramouli: Managing Test and Repair of Embedded Memory Subsystem in SoC. 452

Session C2: Defect-Based Testing

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  Prabhu Krishnamurthy: The Ultimate Chase. 454
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  Vikram Iyengar, Phil Nigh: Defect-Oriented Test for Ultra-Low DPM. 455
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  Hans A. R. Manhaeve: Current Testing for Nanotechnologies: A Demystifying Application Perspective.. 456

Session C4: Advances in Test Generation and Verification

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  Indradeep Ghosh: High Level Test Generation for Custom Hardware: An Industrial Perspective. 458
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  Praveen Parvathala: High Level Test Generation / SW based Embedded Test. 459
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  Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu: Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. 460

Session C5: Test Data Compression and System Level Testing

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  Kedarnath J. Balakrishnan: Emerging Techniques for Test Data Compression. 462
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  Nilanjan Mukherjee: Improving Test Quality Using Test Data Compression. 463
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  Tapan J. Chakraborty: Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. 464-465

Session C6: Mixed Signal Testing

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  Sasikumar Cherubal: Challenges in Next Generation Mixed-Signal IC Production Testing. 466
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  Salem Abdennadher, Saghir A. Shaikh: Practices in Testing of Mixed-Signal and RF SoCs. 467
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  Salem Abdennadher, Saghir A. Shaikh: Challenges in High Speed Interface Testing. 468

Session C7: Delay Testing and Burn-in Test Methodologies

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  Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman: Practical Aspects of Delay Testing for Nanometer Chips. 470
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  T. M. Mak: Limitation of structural scan delay test. 471
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  Mohd Fairuz Zakaria, Zainal Abu Kassim, Melanie Po-Leen Ooi, Serge N. Demidenko: Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST. 472

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