• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 26 matches

• 2000
• 
  Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell:
  Towards an ADC BIST scheme using the histogram test technique. ETW 2000: 53-58
• 
  Ismet Bayraktaroglu, Alex Orailoglu:
  Low cost concurrent test implementation for linear digital systems. ETW 2000: 140-143
• 
  David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
  A method for trading off test time, area and fault coverage in datapath BIST synthesis. ETW 2000: 133-139
• 
  Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
  Hierarchical defect-oriented fault simulation for digital circuits. ETW 2000: 69-74
• 
  Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
  An effective distributed BIST architecture for RAMs. ETW 2000: 119-124
• 
  Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick:
  Combining symbolic and genetic techniques for efficient sequential circuit test generation. ETW 2000: 105-110
• 
  Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York:
  Microprocessor cores. ETW 2000: 17-22
• 
  Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva:
  A system level boundary scan controller board for VME applications [to CERN experiments]. ETW 2000: 153-158
• 
  Anton Chichkov, Dirk Merlier, Peter Cox:
  Current testing procedure for deep submicron devices. ETW 2000: 91-96
• 
  Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
  CA-CSTP: a new BIST architecture for sequential circuits. ETW 2000: 167-172
• 
  Piet Engelke, Bernd Becker, Martin Keim:
  A parameterizable fault simulator for bridging faults. ETW 2000: 63-68
• 
  Antoni Ferré, Joan Figueras:
  LEAP: An accurate defect-free I_DDQ estimator. ETW 2000: 33-38
• 
  Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof:
  Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ETW 2000: 161-166
• 
  Bram Kruseman:
  Comparison of defect detection capabilities of current-based and voltage-based test methods. ETW 2000: 175-180
• 
  Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche:
  Test challenges in nanometer technologies. ETW 2000: 83-90
• 
  Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
  System-level test bench generation in a co-design framework. ETW 2000: 25-30
• 
  Yiorgos Makris, Jamison Collins, Alex Orailoglu:
  How to avoid random walks in hierarchical test path identification. ETW 2000: 111-116
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. ETW 2000: 144-149
• 
  Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
  Analyzing the test generation problem for an application-oriented test of FPGAs. ETW 2000: 75-80
• 
  Masaru Sanada:
  Defect detection from visual abnormalities in manufacturing process using I_DDQ. ETW 2000: 39-44
• 
  Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
  RTL-based functional test generation for high defects coverage in digital SOCs. ETW 2000: 99-104
• 
  Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani:
  Bridging the testing speed gap: design for delay testability. ETW 2000: 3-8
• 
  Daniela De Venuto, Michael J. Ohletz, G. Matarrese:
  Static and dynamic on-chip test response evaluation using a two-mode comparator. ETW 2000: 47-52
• 
  Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
  Delay fault testing: choosing between random SIC and random MIC test sequences. ETW 2000: 9-14
• 
  Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik:
  Compressed bit fail maps for memory fail pattern classification. ETW 2000: 125-130
• 
  5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000. IEEE Computer Society 2000, ISBN 0-7695-0701-8 [contents]