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ORCIDICSAMOS 2009: Samos, Greece
- Walid A. Najjar, Michael J. Schulte:
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, July 20-23, 2009. IEEE 2009, ISBN 978-1-4244-4501-1
Keynotes
- Kari Pulli:
Mobile visual computing. - Grant Martin:
"Slower than you think" - The evolution of processor and SoC architectures.
Reconfigurable Systems
- Ramón José Aliaga
, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch:
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. 1-8 - Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou:
High-speed FPGA-based implementations of a Genetic Algorithm. 9-16 - Daniel Cabrera, Xavier Martorell, Georgi Gaydadjiev, Eduard Ayguadé, Daniel Jiménez-González:
OpenMP extensions for FPGA accelerators. 17-24 - Emmanuel Casseau, Bertrand Le Gal:
High-level synthesis for the design of FPGA-based signal processing systems. 25-32
Instruction Scheduling and Microarchitecture Optimizations
- Nayan V. Mujadiya:
Instruction scheduling for VLIW processors under variation scenario. 33-40 - Elham Safi, Andreas Moshovos, Andreas G. Veneris:
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. 41-48 - Pavlos Petoumenos, Georgios Keramidas, Stefanos Kaxiras:
Instruction-based reuse-distance prediction for effective cache management. 49-58
Simulation and Emulation Techniques
- Sharookh Daruwalla, Resit Sendag, Joshua J. Yi:
Adaptive simulation sampling using an Autoregressive framework. 59-66 - Andreas Genser, Christian Bachmann, Josef Haid, Christian Steger, Reinhold Weiss:
An emulation-based real-time power profiling unit for embedded software. 67-73 - Hoeseok Yang, Youngmin Yi, Soonhoi Ha:
A timed HW/SW coemulation technique for fast yet accurate system verification. 74-81 - A. N. Satrawala, S. K. Nandy:
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. 82-91
Multiprocessor Modeling and Evaluation
- Wolfgang Haid, Matthias Keller, Kai Huang, Iuliana Bacivarov, Lothar Thiele:
Generation and calibration of compositional performance analysis models for multi-processor systems. 92-99 - Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal:
Performance evaluation of concurrently executing parallel applications on multi-processor systems. 100-107 - Jerker Bengtsson, Bertil Svensson:
Manycore performance analysis using timed configuration graphs. 108-117 - Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques. 118-124
Multiprocessor Communication and Synchronization
- Holger Flatt, Ingo Schmädecke, Michael Kärgel, Holger Blume, Peter Pirsch:
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. 125-132 - Mayan Moudgill, Vitaly Kalashnikov, Murugappan Senthilvelan, U. Srikantiah, Tak-po Li, Pablo I. Balzola, John Glossner:
Synchronization on heterogeneous multiprocessor systems. 133-139 - Tjerk Bijlsma, Marco Bekooij, Gerard J. M. Smit:
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs. 140-148 - George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis G. Kavadias, Manolis Katevenis, Dionisios N. Pnevmatikatos, Xiaojun Yang:
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. 149-156
DSP Architectures and Implementations
- Ganesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni:
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. 157-164 - Robert Fasthuber, Min Li, David Novo, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor:
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. 165-171 - Sangwon Seo, Mark Woh, Scott A. Mahlke, Trevor N. Mudge, Sunfaram Vijay, Chaitali Chakrabarti:
Customizing wide-SIMD architectures for H.264. 172-179 - Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen, Yu Hen Hu:
Parallel implementation of convolution encoder for software defined radio on DSP architecture. 180-186
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