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2020 – today
- 2024
[j15]Lucas Deutschmann
, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A Scalable Formal Verification Methodology for Data-Oblivious Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2551-2564 (2024)- [c88]Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann, Dino Mehmedagic, Cristiano Rodrigues, Daniel Oliveira, Mohammad Rahmani Fadiheh, Keerthikumara Devarajegowda, Sandro Pinto, Dominik Stoffel, Wolfgang Kunz:
MCU-Wide Timing Side Channels and Their Detection. DAC 2024: 292:1-292:6 - [c87]Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators. DATE 2024: 1-6 - [c86]Endri Kaja, Nicolas Gerlin, Bihan Zhao, Daniela Sanchez Lopera, Jad Al Halabi, Azam Sher Khan, Sebastian Prebeck, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods. ISQED 2024: 1-8 - [c85]Lucas Deutschmann, Yazan Kazhalawi, Jonathan Seckinger, Anna Lena Duque Antón, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
Data-Oblivious and Performant: On Designing Security-Conscious Hardware. LATS 2024: 1-6 - [i12]Anna Lena Duque Antón, Johannes Müller, Philipp Schmitz, Tobias Jauch, Alex Wezel, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL. CoRR abs/2407.18679 (2024) - 2023
- [j14]Anna Lena Duque Antón, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation. IEEE Access 11: 52695-52711 (2023) - [j13]Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. IEEE Trans. Computers 72(1): 222-235 (2023) - [c84]Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Philipp Schmitz, Sayak Ray, Jason M. Fung, Christopher W. Fletcher, Dominik Stoffel, Wolfgang Kunz:
Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL. ICCAD 2023: 1-9 - [c83]Philipp Schmitz, Johannes Mueller, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz:
UPEC-PN: Exhaustive constant time verification of low-level software using property checking. MBMV 2023: 1-8 - [c82]Dino Mehmedagic, Mohammad Rahmani Fadiheh, Johannes Müller, Anna Lena Duque Antón, Dominik Stoffel, Wolfgang Kunz:
Design of Access Control Mechanisms in Systems-on-Chip with Formal Integrity Guarantees. USENIX Security Symposium 2023: 2779-2796 - [i11]Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A Scalable Formal Verification Methodology for Data-Oblivious Hardware. CoRR abs/2308.07757 (2023) - [i10]Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann, Dino Mehmedagic, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A New Security Threat in MCUs - SoC-wide timing side channels and how to find them. CoRR abs/2309.12925 (2023) - [i9]Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators. CoRR abs/2312.06515 (2023) - [i8]Philipp Schmitz, Tobias Jauch, Alex Wezel, Mohammad Rahmani Fadiheh, Thore Tiemann, Jonah Heller, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz:
Okapi: A Lightweight Architecture for Secure Speculation Exploiting Locality of Memory Accesses. CoRR abs/2312.08156 (2023) - 2022
- [c81]Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
Towards a formally verified hardware root-of-trust for data-oblivious computing. DAC 2022: 727-732 - [c80]Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
MetaFS: Model-driven Fault Simulation Framework. DFT 2022: 1-4 - [c79]Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz:
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation. MBMV 2022: 1-4 - [c78]Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn:
A Framework for Formal Verification of DRAM Controllers. MEMSYS 2022: 6:1-6:7 - [c77]Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection. VLSI-SoC 2022: 1-6 - [c76]Endri Kaja, Nicolas Gerlin, Monideep Bora, Gabriel Rutsch, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker:
Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation. VLSI-SoC 2022: 1-6 - [c75]Stian Gerlach Sørensen, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz:
Generation of Formal CPU Profiles for Embedded Systems. VLSI-SoC 2022: 1-6 - [i7]Lukas Steiner, Chirag Sudarshan, Matthias Jung, Dominik Stoffel, Norbert Wehn:
A Framework for Formal Verification of DRAM Controllers. CoRR abs/2209.14021 (2022) - 2021
- [c74]Johannes Müller, Mohammad Rahmani Fadiheh, Anna Lena Duque Antón, Thomas Eisenbarth, Dominik Stoffel, Wolfgang Kunz:
A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level. DAC 2021: 991-996 - [c73]Christian Bartsch, Stephan Wilhelm, Daniel Kästner, Dominik Stoffel, Wolfgang Kunz:
Compositional Fault Propagation Analysis in Embedded Systems using Abstract Interpretation. ITC 2021: 409-418 - [i6]Karthik Ganesan, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra:
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection. CoRR abs/2106.10392 (2021) - [i5]Mohammad Rahmani Fadiheh, Alex Wezel, Johannes Müller, Jörg Bormann, Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors. CoRR abs/2108.01979 (2021) - 2020
- [j12]Tobias Ludwig, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3093-3106 (2020) - [j11]Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz:
Generation of Abstract Driver Models for IP Integration Verification. IEEE Trans. Emerg. Top. Comput. 8(4): 938-947 (2020) - [c72]Mohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors. DAC 2020: 1-6 - [c71]Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz:
Gap-free Processor Verification by S2QED and Property Generation. DATE 2020: 526-531 - [c70]Thomas Fehmel, Viet-Tan Nguyen, Dominik Stoffel, Wolfgang Kunz:
Automatic State Space Analysis for Modeling Untrusted Embedded Device Drivers. DSD 2020: 109-116 - [c69]M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
Efficient binary-level coverage analysis. ESEC/SIGSOFT FSE 2020: 1153-1164 - [i4]M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
Efficient Binary-Level Coverage Analysis. CoRR abs/2004.14191 (2020)
2010 – 2019
- 2019
- [j10]Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1262-1275 (2019) - [c68]Michael Schwarz, Raphael Stahl, Daniel Müller-Gritschneder, Ulf Schlichtmann, Dominik Stoffel, Wolfgang Kunz:
ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization. DAC 2019: 187 - [c67]Mohammad Rahmani Fadiheh, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra, Wolfgang Kunz:
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking. DATE 2019: 994-999 - [c66]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. DATE 2019: 1000-1005 - [c65]Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
Systematic RISC-V based Firmware Design⋆. FDL 2019: 1-8 - [c64]Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
ACCESS: HW/SW-Co-Equivalence Checking for Firmware Optimization. MBMV 2019: 1-4 - [i3]Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra:
Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study. CoRR abs/1902.01494 (2019) - 2018
- [c63]Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz:
Symbolic quick error detection using symbolic initial state for pre-silicon verification. DATE 2018: 55-60 - [i2]Mohammad Rahmani Fadiheh, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra, Wolfgang Kunz:
Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking. CoRR abs/1812.04975 (2018) - 2017
- [j9]Christian Bartsch, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems. J. Electron. Test. 33(1): 77-92 (2017) - [c62]Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
Cycle-accurate software modeling for RTL verification of embedded systems. DDECS 2017: 103-108 - [c61]M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
goSAT: Floating-point satisfiability as global optimization. FMCAD 2017: 11-14 - [c60]M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
Speculative disassembly of binary code. MBMV 2017: 51-52 - [c59]Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Dynamic Power Optimization based on Formal Property Checking of Operations. MBMV 2017: 129-136 - [c58]Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Dynamic Power Optimization Based on Formal Property Checking of Operations. VLSID 2017: 227-232 - 2016
- [c57]M. Ammar Ben Khadra, Dominik Stoffel, Wolfgang Kunz:
Speculative disassembly of binary code. CASES 2016: 16:1-16:10 - [c56]Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz:
Properties first? a new design methodology for hardware, and its perspectives in safety analysis. ICCAD 2016: 84 - [c55]Christian Bartsch, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
Safety across the HW/SW interface - Can formal methods meet the challenge? ISIC 2016: 1-3 - [c54]Christian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
A HW-dependent software model for cross-layer fault analysis in embedded systems. LATS 2016: 153-158 - [c53]Christian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
A HW-dependent Software Model for Cross-Layer Fault Analysis in Embedded Systems. MBMV 2016: 10-21 - [c52]Oliver Marx, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
A computer-algebraic approach to formal verification of data-centric low-level software. MEMOCODE 2016: 34-42 - 2015
- [c51]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Architectural system modeling for correct-by-construction RTL design. FDL 2015: 90-97 - [c50]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Architectural System Modeling for Correct-by-Construction RTL Design. MBMV 2015: 93-104 - 2014
- [j8]Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 291-304 (2014) - [c49]Binghao Bao, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz:
A property language for the specification of hardware-dependent embedded system software. FDL 2014: 1-8 - [c48]Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Coverage of compositional property sets under reactive constraints. ISQED 2014: 589-596 - [c47]Carlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz:
Software in a hardware view: New models for HW-dependent software in SoC verification and test. ITC 2014: 1-9 - [c46]Christian Bartsch, Carlos Villarraga, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz:
Efficient SAT/simulation-based model generation for low-level embedded software. MBMV 2014: 147-157 - [c45]Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl:
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology. SoCC 2014: xlv-xlvi - 2013
- [j7]Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Jörg Bormann, Markus Wedler, Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz:
A New Formal Verification Approach for Hardware-dependent Embedded System Software. IPSJ Trans. Syst. LSI Des. Methodol. 6: 135-145 (2013) - [c44]Bernard Schmidt, Carlos Villarraga, Jörg Bormann, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
A computational model for SAT-based verification of hardware-dependent low-level embedded system software. ASP-DAC 2013: 711-716 - [c43]Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer:
Proof logging for computer algebra based SMT solving. ICCAD 2013: 677-684 - [c42]Bernard Schmidt, Carlos Villarraga, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann:
A Hardware-Dependent Model for SAT-based Verification of Interrupt-Driven Low-level Embedded System Software. MBMV 2013: 49-60 - [c41]Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Compositional Completeness over reactive Constraints. MBMV 2013: 83-96 - [c40]Oliver Marx, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer:
Proof Logging for Computer Algebra based SMT Solving. MBMV 2013: 255-265 - [c39]Carlos Villarraga, Bernard Schmidt, Jörg Bormann, Christian Bartsch, Dominik Stoffel, Wolfgang Kunz:
An equivalence checker for hardware-dependent embedded system software. MEMOCODE 2013: 119-128 - [c38]Joakim Urdahl, Shrinidhi Udupi, Dominik Stoffel, Wolfgang Kunz:
Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design. PATMOS 2013: 67-74 - 2012
- [c37]Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
System verification of concurrent RTL modules by compositional path predicate abstraction. DAC 2012: 334-343 - [c36]Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Formal Plausibility Checks for Environment Constraints. FDL (Selected Papers) 2012: 1-16 - [c35]Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Formal plausibility checks for environment constraints. FDL 2012: 13-19 - 2011
- [c34]Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Formal hardware/software co-verification by interval property checking with abstraction. DAC 2011: 510-515 - [c33]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel:
STABLE: A new QF-BV SMT solver for hard verification problems combining Boolean reasoning with computer algebra. DATE 2011: 155-160 - [c32]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Alexander Dreyer, Frank Seelisch, Gert-Martin Greuel:
STABLE: A new QF-BV SMT Solver for hard Verification Problems combining Boolean Reasoning with Computer Algebra. MBMV 2011: 51-60 - [c31]Minh D. Nguyen, Markus Wedler, Bernard Schmidt, Dominik Stoffel, Wolfgang Kunz:
Formal Hardware/Software Co-Verification by Interval Property Checking with Abstraction. MBMV 2011: 61-70 - 2010
- [c30]Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Jörg Bormann, Wolfgang Kunz:
Analyzing k-step induction to compute invariants for SAT-based property checking. DAC 2010: 176-181 - [c29]Sacha Loitz, Markus Wedler, Dominik Stoffel, Christian Brehm, Norbert Wehn, Wolfgang Kunz:
Complete Verification of Weakly Programmable IPs against Their Operational ISA Model. FDL 2010: 29-36 - [c28]Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz:
Path predicate abstraction by complete interval property checking. FMCAD 2010: 207-215 - [c27]Max Thalmaier, Minh D. Nguyen, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Analyzing k-step induction to compute invariants for SAT-based property checking. MBMV 2010: 87-96
2000 – 2009
- 2009
- [c26]Dominik Stoffel:
Formal Verification of Systems-on-Chip - Industrial Experiences and Scientific Perspectives. DEXA Workshops 2009: 3 - [c25]Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Jörg Bormann:
A re-use methodology for formal SoC protocol compliance verification. FDL 2009: 1-6 - [c24]Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
A Re-Use Methodology for SoC Protocol Compliance Verification. MBMV 2009: 57-66 - [i1]Markus Wedler, Evgeny Pavlenko, Alexander Dreyer, Frank Seelisch, Dominik Stoffel, Gert-Martin Greuel, Wolfgang Kunz:
Solving hard instances in QF-BV combining Boolean reasoning with computer algebra. Algorithms and Applications for Next Generation SAT Solvers 2009 - 2008
- [j6]Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz:
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2068-2082 (2008) - [c23]Oliver Wienand, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Gert-Martin Greuel:
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths. CAV 2008: 473-486 - [c22]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev:
Modeling of Custom-Designed Arithmetic Components for ABL Normalization. FDL 2008: 124-129 - [c21]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev:
A New Verification Technique for Custom-Designed Components at the Arithmetic Bit Level. FDL (Selected Papers) 2008: 257-272 - [c20]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev:
Modeling of Custom-Designed Arithmetic Components for ABL Normalization. MBMV 2008: 51-60 - 2007
- [j5]Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz:
A Normalization Method for Arithmetic Data-Path Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1909-1922 (2007) - [c19]Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Arithmetic Constraints in SAT-based Property Checking. MBMV 2007: 91-100 - 2005
- [c18]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Normalization at the arithmetic bit level. DAC 2005: 457-462 - [c17]Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz:
Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal. GI Jahrestagung (1) 2005: 303-307 - [c16]Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz:
Transition-by-transition FSM traversal for reachability analysis in bounded model checking. ICCAD 2005: 1068-1075 - 2004
- [j4]Dominik Stoffel, Wolfgang Kunz:
Equivalence checking of arithmetic circuits on the arithmetic bit level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 586-597 (2004) - [j3]Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz:
Structural FSM traversal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 598-619 (2004) - [c15]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Exploiting state encoding for invariant generation in induction-based property checking. ASP-DAC 2004: 424-429 - [c14]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Arithmetic Reasoning in DPLL-Based SAT Solving. DATE 2004: 30-35 - [c13]Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey:
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor. DATE 2004: 162-167 - [c12]Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353 - [c11]Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. MBMV 2004: 24-33 - [e1]Dominik Stoffel, Wolfgang Kunz:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, Germany, February 24-25, 2004. Shaker 2004 [contents] - 2003
- [c10]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Using RTL Statespace Information and State Encoding for Induction Based Property Checking. DATE 2003: 11156-11157 - [c9]Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey:
Cost-efficient Formal Block Verification for ASIC Design. MBMV 2003: 184-188 - [c8]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Towards the impact of state encoding on induction-based property checking. MBMV 2003: 199-208 - 2002
- [c7]Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. ISVLSI 2002: 151-158 - 2001
- [j2]Wolfgang Kunz, Dominik Stoffel:
Äquivalenzvergleich mit strukturellen Methoden (Equivalence Checking using Structural Methods). Informationstechnik Tech. Inform. 43(1): 8-15 (2001) - [c6]Dominik Stoffel, Wolfgang Kunz:
Verification of Integer Multipliers on the Arithmetic Bit Level. ICCAD 2001: 183-189 - [c5]Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz:
Cycle time optimization by timing driven placement with simultaneous netlist transformations. ISCAS (5) 2001: 359-362
1990 – 1999
- 1999
- [b2]Dominik Stoffel:
Formal verification of sequential circuits using reasoning techniques. Goethe University Frankfurt, Frankfurt am Main, Germany, 1999 - [c4]Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz:
Accelerating Boolean Implications with FPGAs. FPL 1999: 532-537 - [c3]Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz:
Cell replication and redundancy elimination during placement for cycle time optimization. ICCAD 1999: 25-30 - 1997
- [b1]Wolfgang Kunz, Dominik Stoffel:
Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques. Frontiers in electronic testing, Springer 1997, ISBN 978-0-7923-9921-6, pp. I-XV, 1-230 - [j1]Wolfgang Kunz, Dominik Stoffel, Prem R. Menon:
Logic optimization and equivalence checking by implication analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 266-281 (1997) - [c2]Dominik Stoffel, Wolfgang Kunz, Stefan Gerber:
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks. ASP-DAC 1997: 529-538 - [c1]Dominik Stoffel, Wolfgang Kunz:
Record & play: a structural fixed point iteration for sequential circuit verification. ICCAD 1997: 394-399
Coauthor Index
[j15] [c88] [c87] [c86] [c85] [i12] [j14] [j13] [c84] [c83] [c82] [i11] [i10] [i9] [i8] [c81] [c80] [c79] [c77] [c76] [c75] [c74] [c73] [i6] [i5] [j12] [j11] [c72] [c71] [c70] [c69] [i4] [j10] [c68] [c67] [c66] [c65] [c64] [i3] [c63] [i2] [j9] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [j8] [c49] [c48] [c47] [c46] [c45] [j7] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c25] [c24] [i1] [j6] [c23] [c22] [c21] [c20] [j5] [c19] [c18] [c17] [c16] [j4] [j3] [c15] [c14] [c12] [c11] [e1] [c10] [c8] [c7] [j2] [c6] [c5] [c4] [c3] [b1] [j1] [c2] [c1]
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