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ORCIDJieh-Tsorng Wu
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2020 – today
- 2023
[c19]Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin
, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC 2023: 352-357- [c18]Ding-Hao Wang, Jieh-Tsorng Wu:
A Digital Jitter Compensation Technique for Analog-to-Digital Converters. ISCAS 2023: 1-5 - 2021
- [j26]Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Yong Qu, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang:
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. IEEE J. Solid State Circuits 56(8): 2347-2359 (2021)
2010 – 2019
- 2019
- [j25]Sheng-Hui Liao, Jieh-Tsorng Wu:
A 1-V 175- $\mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques. IEEE J. Solid State Circuits 54(9): 2523-2531 (2019) - [c17]Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang:
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch. ESSCIRC 2019: 83-86 - 2018
- [c16]Sheng-Hui Liao, Jieh-Tsorng Wu:
A 1 V 175 μW 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques. CICC 2018: 1-4 - 2017
- [j24]Chih-Min Chang, Jieh-Tsorng Wu:
A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1106-1117 (2017) - 2016
- [c15]Chih-Min Chang, Jieh-Tsorng Wu:
A computationally-efficient PWM technique for digital class-D amplifiers. ISCAS 2016: 1946-1949 - 2015
- [j23]Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynänen, Kenichi Okada, Jaeha Kim:
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 50(12): 2799-2803 (2015) - [j22]Yung-Hui Chung, Jieh-Tsorng Wu:
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 557-566 (2015) - 2013
- [j21]Bing-Nan Fang, Jieh-Tsorng Wu:
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation. IEEE J. Solid State Circuits 48(3): 670-683 (2013) - [j20]Su-Hao Wu, Jieh-Tsorng Wu:
A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. IEEE J. Solid State Circuits 48(9): 2170-2179 (2013) - [c14]Chia-Ling Chang, Jieh-Tsorng Wu:
A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator. ISCAS 2013: 813-816 - [c13]Boris Murmann, Jafar Savoj, Piet Wambacq, Jieh-Tsorng Wu:
F6: Mixed-signal/RF design and modeling in next-generation CMOS. ISSCC 2013: 510-511 - [c12]Su-Hao Wu, Jieh-Tsorng Wu:
Background calibration of integrator leakage in discrete-time delta-sigma modulators. NEWCAS 2013: 1-4 - 2012
- [j19]Yun Chai, Jieh-Tsorng Wu:
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC. IEEE J. Solid State Circuits 47(12): 2905-2915 (2012) - [c11]Bing-Nan Fang, Jieh-Tsorng Wu:
A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps. ISCAS 2012: 1042-1045 - [c10]Yun Chai, Jieh-Tsorng Wu:
A 5.37mW 10b 200MS/s dual-path pipelined ADC. ISSCC 2012: 462-464 - 2011
- [j18]Chun-Cheng Huang, Chung-Yi Wang, Jieh-Tsorng Wu:
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques. IEEE J. Solid State Circuits 46(4): 848-858 (2011) - [j17]Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu:
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz. IEEE J. Solid State Circuits 46(12): 2845-2856 (2011) - [j16]Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu:
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. IEEE Trans. Circuits Syst. II Express Briefs 58-II(1): 1-5 (2011) - [c9]Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu:
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. ISSCC 2011: 192-194 - 2010
- [j15]Yung-Hui Chung, Jieh-Tsorng Wu:
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. IEEE J. Solid State Circuits 45(11): 2217-2226 (2010) - [c8]Chi-Wei Fan, Jieh-Tsorng Wu:
ADC clock jitter measurement and correction using a stochastic TDC. APCCAS 2010: 1007-1010
2000 – 2009
- 2009
- [j14]Chung-Yi Wang, Jieh-Tsorng Wu:
A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(6): 1102-1114 (2009) - [j13]Chi-Wei Fan, Jieh-Tsorng Wu:
Jitter Measurement and Compensation for Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. 58(11): 3874-3884 (2009) - 2007
- [j12]Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration. IEEE J. Solid State Circuits 42(10): 2149-2160 (2007) - [j11]Jen-Lin Fan, Chung-Yi Wang, Jieh-Tsorng Wu:
A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(6): 1213-1223 (2007) - 2006
- [j10]Chung-Yi Wang, Jieh-Tsorng Wu:
A background timing-skew calibration technique for time-interleaved analog-to-digital converters. IEEE Trans. Circuits Syst. II Express Briefs 53-II(4): 299-303 (2006) - [j9]Ju-Ming Chou, Yu-Tang Hsieh, Jieh-Tsorng Wu:
Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 984-991 (2006) - [c7]Zwei-Mei Lee, Cheng-Yeh Wang, Jieh-Tsorng Wu:
A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration. CICC 2006: 209-212 - 2005
- [j8]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 40(5): 1047-1056 (2005) - [j7]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration". IEEE J. Solid State Circuits 40(11): 2339 (2005) - [j6]Chun-Cheng Huang, Jieh-Tsorng Wu:
A background comparator calibration technique for flash analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1732-1740 (2005) - [c6]Jen-Lin Fan, Jieh-Tsorng Wu:
A robust background calibration technique for switched-capacitor pipelined ADCs. ISCAS (2) 2005: 1374-1377 - 2004
- [c5]Chun-Cheng Huang, Jieh-Tsorng Wu:
A statistical background calibration technique for flash analog-to-digital converters. ISCAS (1) 2004: 125-128 - [c4]Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang:
Multi-level memory systems using error control codes. ISCAS (2) 2004: 393-396 - 2003
- [j5]Cheng-Chung Hsu, Jieh-Tsorng Wu:
A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier. IEEE J. Solid State Circuits 38(10): 1663-1670 (2003) - [c3]Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A digital background calibration technique for pipelined analog-to-digital converters. ISCAS (1) 2003: 881-884 - 2001
- [c2]Cheng-Chung Hsu, Jieh-Tsorng Wu:
Highly linear 100 MHz CMOS programmable gain amplifiers. ISCAS (1) 2001: 647-650
1990 – 1999
- 1999
- [j4]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V, 1.8-GHz BJT phase-locked loop. IEEE J. Solid State Circuits 34(6): 784-789 (1999) - 1998
- [j3]Jieh-Tsorng Wu, Kuen-Long Chang:
MOS charge pumps for low-voltage operation. IEEE J. Solid State Circuits 33(4): 592-597 (1998) - [j2]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2-V 2-GHz BJT variable frequency oscillator. IEEE J. Solid State Circuits 33(9): 1406-1410 (1998) - [c1]Wei-Zen Chen, Jieh-Tsorng Wu:
A 2 V 1.6 GHz BJT phase-locked loop. CICC 1998: 563-566
1980 – 1989
- 1988
- [j1]Jieh-Tsorng Wu, Bruce A. Wooley:
A 100-MHz pipelined CMOS comparator. IEEE J. Solid State Circuits 23(6): 1379-1385 (1988)
Coauthor Index
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