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ORCIDShmuel Wimer
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Journal Articles
- 2023
[j40]Binyamin Frankel
, Shmuel Wimer:
A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories. IEEE Trans. Computers 72(2): 513-519 (2023)- [j39]Binyamin Frankel, Eyal Sarfati, Davide Rossi, Shmuel Wimer:
Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1605-1612 (2023) - 2021
- [j38]Nir Halman, Shmuel Wimer:
Resource allocation in rooted trees subject to sum constraints and nonlinear cost functions. Inf. Process. Lett. 170: 106114 (2021) - 2018
- [j37]Roi Herman, Binyamin Frankel, Shmuel Wimer:
Optimal queuing-based memory refreshing algorithm for energy efficient processors. Comput. Electr. Eng. 71: 505-514 (2018) - [j36]Binyamin Frankel, Roi Herman, Shmuel Wimer:
Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors. IEEE Trans. Computers 67(9): 1331-1340 (2018) - [j35]Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer:
Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3435-3444 (2018) - 2017
- [j34]Eyal Sarfati, Binyamin Frankel, Yitzhak Birk, Shmuel Wimer:
Optimal VLSI Delay Tuning by Space Tapering With Clock-Tree Application. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 2160-2170 (2017) - [j33]Doron Gluzer, Shmuel Wimer:
Probability-Driven Multibit Flip-Flop Integration With Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1173-1177 (2017) - 2016
- [j32]Amir Albeck, Shmuel Wimer:
Energy efficient computing by multi-mode addition. Integr. 55: 176-182 (2016) - [j31]Shmuel Wimer:
Optimal weight allocation in rooted trees. J. Comb. Optim. 31(3): 1023-1033 (2016) - [j30]Binyamin Frankel, Shmuel Wimer:
Optimal VLSI Delay Tuning by Wire Shielding. J. Optim. Theory Appl. 170(3): 1060-1067 (2016) - [j29]Amit Kazimirsky, Shmuel Wimer:
Opportunistic Refreshing Algorithm for eDRAM Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1921-1932 (2016) - 2015
- [j28]Shmuel Wimer, Amnon Stanislavsky:
Energy efficient hybrid adder architecture. Integr. 48: 109-115 (2015) - [j27]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48: 116-128 (2015) - [j26]Yakov Kaplan, Shmuel Wimer:
Mixing Drivers in Clock-Tree for Power Supply Noise Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1382-1391 (2015) - 2014
- [j25]Shmuel Wimer, Amir Albeck, Israel Koren:
A low energy dual-mode adder. Comput. Electr. Eng. 40(5): 1524-1537 (2014) - [j24]Shmuel Wimer:
Easy and difficult exact covering problems arising in VLSI power reduction by clock gating. Discret. Optim. 14: 104-110 (2014) - [j23]Shmuel Wimer:
Planar CMOS to multi-gate layout conversion for maximal fin utilization. Integr. 47(1): 115-122 (2014) - [j22]Eugene Shaphir, Ron Y. Pinter, Shmuel Wimer:
Cell-based interconnect migration by hierarchical optimization. Integr. 47(2): 161-174 (2014) - [j21]Shmuel Wimer, Doron Gluzer, Uri Wimer:
Using well-solvable minimum cost exact covering for VLSI clock energy minimization. Oper. Res. Lett. 42(5): 332-336 (2014) - [j20]Shmuel Wimer, Arye Albahari:
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1465-1472 (2014) - [j19]Itamar Levi, Amir Albeck, Alexander Fish, Shmuel Wimer:
A Low Energy and High Performance ${\rm DM}^{2}$ Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3175-3183 (2014) - [j18]Shmuel Wimer, Israel Koren:
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 771-778 (2014) - 2013
- [j17]Shmuel Wimer:
On optimal flip-flop grouping for VLSI power minimization. Oper. Res. Lett. 41(5): 486-489 (2013) - 2012
- [j16]Ben Emanuel, Shmuel Wimer, Gershon Wolansky:
Using well-solvable quadratic assignment problems for VLSI interconnect applications. Discret. Appl. Math. 160(4-5): 525-535 (2012) - [j15]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23(2): 292-300 (2012) - [j14]Shmuel Wimer, Israel Koren:
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1772-1780 (2012) - 2011
- [j13]Eranda Çela, Nina S. Schmuck, Shmuel Wimer, Gerhard J. Woeginger:
The Wiener maximum quadratic assignment problem. Discret. Optim. 8(3): 411-416 (2011) - 2010
- [j12]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1650-1654 (2010) - 2009
- [j11]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14(4): 55:1-55:28 (2009) - 2008
- [j10]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles. Integr. 41(2): 253-268 (2008) - [j9]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): 65:1-65:17 (2008) - 2006
- [j8]Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny:
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1089-1100 (2006) - 1993
- [j7]Shmuel Wimer, Israel Koren, Israel Cederbaum:
On Paths with the Shortest Average Arc Length in Weighted Graphs. Discret. Appl. Math. 45(2): 169-179 (1993) - [j6]Jack A. Feldman, Israel A. Wagner, Shmuel Wimer:
An efficient algorithm for some multirow layout problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1178-1185 (1993) - 1992
- [j5]Israel Cederbaum, Israel Koren, Shmuel Wimer:
Balanced Block Spacing for VLSI Layout. Discret. Appl. Math. 40(3): 303-318 (1992) - 1989
- [j4]Shmuel Wimer, Israel Koren, Israel Cederbaum:
Optimal aspect ratios of building blocks in VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 139-145 (1989) - [j3]Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer:
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7): 737-743 (1989) - 1988
- [j2]Shmuel Wimer, Israel Koren:
Analysis of strategies for constructive general block placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 371-377 (1988) - 1987
- [j1]Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman:
Optimal Chaining of CMOS Transistors in a Functional Cell. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 795-801 (1987)
Conference and Workshop Papers
- 2016
- [c7]Shmuel Wimer, Israel Koren:
Energy efficient deeply fused dot-product multiplication architecture. ASAP 2016: 115-122 - 2011
- [c6]Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer:
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD 2011: 39-46 - 2010
- [c5]Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160 - 2006
- [c4]Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006 - 2004
- [c3]Shay Michaely, Shmuel Wimer, Avinoam Kolodny:
Optimal resizing of bus wires in layout migration. ICECS 2004: 411-414 - 1988
- [c2]Shmuel Wimer, Israel Koren, Israel Cederbaum:
Optimal Aspect Ratios of Building Blocks in VLSI. DAC 1988: 66-72 - 1983
- [c1]Shmuel Wimer, N. Sharfman:
HOPLA-PLA optimization and synthesis. DAC 1983: 790-794
Coauthor Index
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