default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID20th DAC 1983: Miami Beach, Florida, USA
- Charles E. Radke:
Proceedings of the 20th Design Automation Conference, DAC '83, Miami Beach, Florida, USA, June 27-29, 1983. ACM/IEEE 1983, ISBN 0-8186-0026-8 - John S. Mayo:
Design automation - lessons of the past, challenges for the future. 1-2 - Robert J. Camoin:
Central DA and its role: An executive view. 3 - Winfried Hahn:
Computer Design Language - Version Munich (CDLM) a modern multi-level language. 4-11 - Peter Robinson, Jeremy Dion:
Programmimg languages for hardware description. 12-16 - Karl J. Lieberherr, Svend E. Knudsen:
Zeus: A hardware description language for VLSI. 17-23 - Adam Pawlak:
Microprocessor systems modeling with MODLAN. 24 - Randy H. Katz, Shlomo Weiss:
Chip assemblers: Concepts and capabilities. 25-30 - Jonathan B. Rosenberg, David G. Boyer, John A. Dallen, Stephen W. Daniel, Charles J. Poirier, John Poulton, C. Durward Rogers, Neil Weste:
A vertically integrated VLSI design environment. 31-38 - K. Ahdoot, Rita R. Alvarodiaz, L. Crawley:
IBM FSD VLSI chip design methodology. 39-45 - N. J. Elias, Arthur W. Wetzel:
The IC Module Compiler, a VLSI system design aid. 46-49 - Kuang-Wei Chiang, Zvonko G. Vranesic:
On fault detection in CMOS logic networks. 50-56 - Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto:
A new integrated system for PLA testing and verification. 57-63 - Sunil K. Jain, Vishwani D. Agrawal:
Test generation for MOS circuits using D-algorithm. 64-70 - Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara:
Test generation for scan design circuits with tri-state modules and bidirectional terminals. 71-78 - Steve Sapiro:
Engineering Workstations: Tools or toys? 79-80 - J. Robert Logan:
Design/synthesis workshop session. 81-82 - John A. Board Jr., Peter N. Marinos:
An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator - PARSIM). 83-92 - Andrew Sangster, John Monahan:
Aquarius: Logic simulation on an Engineering Workstation. 93-99 - Piet Stevens, Guido Arnout:
BIMOS, an MOS oriented multi-level logic simulator. 100-106 - Yuh-Zen Liao, Chak-Kuen Wong:
An algorithm to compact a VLSI symbolic layout with mixed constraints. 107-112 - Gershon Kedem, Hiroyuki Watanabe:
Graph-optimization techniques for IC layout and compaction. 113-120 - Werner L. Schiele:
Improved compaction by minimized length of wires. 121-127 - Hriday R. Prasad:
Tutorial - Group Technology. 128 - F. W. Day:
Computer Aided Software Engineering (CASE). 129-136 - Charles L. Leath, Steven J. Ollanik:
Software architecture for the implementation of a Computer-Aided Engineering system. 137-142 - David Kramlich, Gretchen P. Brown, Richard T. Carling, Christopher F. Herot:
Program visualization: Graphics support for software development. 143-149 - Tohru Sasaki, Nobuhiko Koike, Kenji Ohmori, Kyoji Tomita:
HAL: A block level HArdware Logic simulator. 150-156 - Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo:
Simulating pass transistor circuits using logic simulation machines. 157-163 - Kenneth J. Supowit, Eric A. Slutz:
Placement algorithms for custom VLSI. 164-170 - Alexander Iosupovicz, Clarence King, Melvin A. Breuer:
A module interchange placement machine. 171-174 - Tokinori Kozawa, Hidekazu Terai, Tatsuki Ishii, Michiyoshi Hayase, Chihei Miura, Yasushi Ogawa, Kuniaki Kishida, Norio Yamada, Yasuhiro Ohno:
Automatic placement algorithms for high packing density V L S I. 175-181 - Dah-Juh Chyan, Melvin A. Breuer:
A placement algorithm for array processors. 182-188 - Francine S. Frome:
Incorporating the human factor in color CAD systems. 189-195 - Nandakumar N. Tendolkar:
Diagnosis of TCM failures in the IBM 3081 Processor complex. 196-200 - E. Kofi Vida-Torku, Charles E. Radke:
Quality level and fault coverage for multichip modules. 201-206 - Kwok-Woon Lai, Daniel P. Siewiorek:
Functional testing of digital systems. 207-213 - Miron Abramovici, Prem R. Menon, David T. Miller:
Critical path tracing - an alternative to fault simulation. 214-220 - Zerksis D. Umrigar, Vijay Pitchumani:
Formal verification of a real-time hardware design. 221-227 - Anthony S. Wojcik:
Formal design verification of digital systems. 228-234 - Robert Brian Cutler:
Automating mask layout and specification panel session. 235-236 - Larry N. Dunn:
An overview of the design and verification subsystem of the Engineering Design System. 237-238 - Frank Rubin, Paul W. Horstmann:
A logic design front-end for improved engineering productivity. 239-245 - C. J. Rimkus, Michael R. Wayne, D. D. Cheng, F. J. Magistro:
Structured design verification: Function and timing. 246-252 - J. B. Bendas:
Design through transformation. 253-256 - Hans-Jürgen Rothermel, Dieter A. Mlynski:
Routing method for VLSI design using irregular cells. 257-262 - Kenneth J. Supowit:
Reducing channel density in standard cell layout. 263-269 - Robert N. Mayo, John K. Ousterhout:
Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool. 270-276 - James R. Warner:
Importance of device independence to the CADCAM industry. 277-278 - Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara:
A multiple media delay simulator for MOS LSI circuits. 279-285 - Patrick Kozak, Ajoy K. Bose, A. Gupta:
Design aids for the simulation of bipolar gate arrays. 286-292 - Vijaya Ramachandran:
An improved switch-level simulator for MOS circuits. 293-299 - Dilip K. Bhavsar:
Design For Test Calculus: An algorithm for DFT rules checking. 300-307 - C. Benmehrez, John F. McDonald:
Measured performance of a programmed implementation of the subscripted D-Algorithm. 308-315 - Charles Paulson:
Classes of diagnostic tests. 316-322 - E. Kofi Vida-Torku, Beverly Messick Huey:
Petri Net based search directing heuristics for test generation. 323-330 - Mark Hofmann, Ulrich Lauther:
HEX: An instruction-driven approach to feature extraction. 331-336 - Gary M. Tarolli, William J. Herman:
Hierarchical circuit extraction with detailed parasitic capacitance. 337-345 - J. D. Bastian, M. Ellement, Priscilla J. Fowler, C. E. Huang, Lawrence P. McNamee:
Symbolic Parasitic Extractor for Circuit Simulation (SPECS). 346-352 - Erich Barke:
A layout verification system for analog bipolar integrated circuits. 353-359 - Shinji Tokumasu, Yoshio Kunitomo, Yoshimi Ohta, Shigeru Yamamoto, Norihiro Nakajima:
Solid model in geometric modelling system: HICAD. 360-366 - Yung-Chia Lee, King-Sun Fu:
Integration of solid modeling and data base management for CAD/CAM. 367-373 - Carlo H. Séquin, Paul S. Strauss:
UNIGRAFIX. 374-381 - M. Bouyat, H. Botta, J. C. Vignat:
VERDI: A computer aided design system for development and city planning. 382-385 - Ronald Waxman, Melvin F. Heilweil, Tom Reinke, Robert J. Smith, Gayla J. Von Ehr:
Workshop - technology design rules for design automation. 387-388 - Melvin F. Heilweil:
Technology rules- the other side of technology dependent code. 389 - Robert J. Smith:
Technology-independent circuit layout. 390-393 - Thomas R. Reinke:
Technology design rules - a user's perspective. 394 - Gayla J. Von Ehr:
Position paper role of technology design rules in Design Automation. 395 - James H. Shelly, David R. Tryon:
Statistical techniques of timing verification. 396-402 - Eiji Tamura, Kimihiro Ogawa, Toshio Nakano:
Path delay analysis for hierarchical building block layout system. 403-410 - Norman P. Jouppi:
Timing analysis for nMOS VLSI. 411-418 - John J. Granacki, Alice C. Parker:
The effect of register-transfer design tradeoffs on chip area and performance. 419-424 - David C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas:
VGAUA: The Variable Geometry Automated Universal Array layout System. 425-429 - M. W. Stebnisky, M. J. McGinnis, Joseph C. Werbickas, Rathin Putatunda, A. Feller:
APSS: An automatic PLA synthesis system. 430-435 - Mikko Tervonen, Hannu Lehikoinen, Timo Mukari:
Integrated computer aided design, documentation and manufacturing system for PCB electronics. 436-443 - John D. Litke:
"Minimizing PWB NC drilling". 444-447 - J. Drier:
Simplification of CNC programming for PWB routing. 448 - Gotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu:
Partitioning and placement technique for bus-structured PWB. 449-456 - Sungho Kang:
Linear ordering and application to placement. 457-464 - Kunio Fukunaga, Shoichiro Yamada, Harold S. Stone, Tamotsu Kasai:
Placement of circuit modules using a graph space approach. 465-471 - Michael C. McFarland:
Computer-aided partitioning of behavioral hardware descriptions. 472-478 - Thaddeus J. Kowalski, Donald E. Thomas:
The VLSI Design Automation Assistant: Prototype system. 479-483 - Charles Y. Hitchcock III, Donald E. Thomas:
A method of automatic data path synthesis. 484-489 - Chia-Jeng Tseng, Daniel P. Siewiorek:
Facet: A procedure for the automated synthesis of digital systems. 490-496 - Charles W. Rose, Greg M. Ordy, Frederic I. Parke:
N.mPc: A retrospective. 497-505 - Roy L. Druian:
Functional models for VLSI design. 506-514 - Raymond Cheng, Brian Griffin, Kun Katsumata, John Welsh:
Functional simulation shortens the development cycle of a new computer. 515-519 - Greg M. Ordy, Charles W. Rose:
The N.2 System. 520-526 - Paul Bassett:
Computer Aided Programming. 527-529 - Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli:
PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays. 530-537 - Wentai Liu, Daniel E. Atkins:
Bounds on the saved area ratio due to PLA folding. 538-544 - Jorge Martínez-Carballido, V. Michael Powers:
PRONTO: Quick PLA product reduction. 545-552 - T. C. Hu, Yue-Sun Kuo:
Optimum reduction of programmable logic array. 553-558 - Ernest L. Hall:
Robots in design (Panel Discussion). 559 - James Cohoon, Sartaj Sahni:
Heuristics for the Circuit Realization Problem. 560-566 - Jose S. Metos, John V. Oldfield:
Binary Decision Diagrams: From abstract representations to physical implementations. 567-570 - Henry L. Nattrass, Glen K. Okita:
Some Computer Aided Engineering System design principles. 571-577 - Chi-Ping Hsu:
General river routing algorithm. 578-583 - Hon Wai Leong, C. L. Liu:
A new channel routing problem. 584-590 - Michael Burstein, Richard N. Pelavin:
Hierarchical channel router. 591-597 - Stanley Wong:
The relational data model for CAD(Tutorial/Panel/Workshop): Close encounters of the third normal form. 598 - Mark N. Haynie:
Tutorial: The relational data model for Design Automation. 599-607 - Dwight D. Hill:
Edisim and Edicap: Graphical simulator interfaces. 608-614 - Peter Flake, Philip Moorby, Gerry Musgrave:
An algebra for logic strength simulation. 615-618 - Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose:
A data structure for MOS circuits. 619-624 - Al Dewey:
VHSIC hardware description (VHDL) development program. 625-628 - J. R. Grierson, B. Cosgrove, Daniel Richert, R. E. Halliwell, Harold Kirk, John C. Knight, John A. McLean, J. M. McGrail, C. O. Newton:
The UK5000 - successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test. 629-636 - Harold Kirk, P. D. Crowhurst, J. A. Skingley, J. Dan Bowman, G. L. Taylor:
Placement of irregular circuit elements on non-uniform gate arrays. 637-643 - B. D. Prazic, M. A. Bozier:
Automatic routing of double layer gate arrays using a moving cursor. 644-650 - C. O. Newton, Patricia A. Young:
Optimisation of global routing for the UK5000 gate array by iteration. 651-657 - Peter Robinson:
Automatic layout for gate arrays with one layer of metal. 658-664 - Howard E. Krohn:
An over-cell gate array channel router. 665-670 - Abbas El Gamal, Zahir A. Syed:
A new statistical model for gate array routing. 671-674 - P. Jennings:
A topology for semicustom array-structured LSI devices, and their automatic customisation. 675-681 - Neil DalCero:
Automatic batch processing in multilayer ceramic metallization. 682-685 - Richard L. Simon:
CAD/CAM - the foundation for Computer Integrated Manufacturing. 686-700 - Sunil K. Jain, Alfred K. Susskind:
Test strategy for microprocessers. 703-708 - Ernst G. Ulrich:
A design verification methodology based on concurrent simulation and clock suppression. 709-712 - Andrea S. LaPaugh, Richard J. Lipton:
Total stuct-at-fault testing by circuit transformation. 713-716 - John M. Acken:
Testing for bridging faults (shorts) in CMOS circuits. 717-718 - Gregory D. Jordan, Brij B. Popli:
ILS - interactive logic simulator. 719-720 - Anoop Gupta:
ACE: A Circuit Extractor. 721-725 - Akira Tsukizoe, Jun'ya Sakemi, Tokinori Kozawa, Hiroshi Fukuda:
MACH : a high-hitting pattern checker for VLSI mask data. 726-731 - Ning-Sang Chang, Ravi Apte:
Consistency checking for MOS/VLSI circuits. 732-733 - Thomas G. Szymanski, Christopher J. Van Wyk:
Space efficient algorithms for VLSI artwork analysis. 734-739 - Ralph McGarity, Daniel P. Siewiorek:
Experiments with the SLIM Circuit Compactor. 740-746 - André Leblond:
CAF: A computer-assisted floorplanning tool. 747-753 - Anderew S. Moulton:
Laying the power and ground wires on a VLSI chip. 754-755 - Rossane Wyleczuk, Lynn Meyer, Gigi Babcock:
The Transfer of University Software for Industry Use. 756-761 - Carlo Batini, C. Costa:
A graphical tool for conceptual design of data base applications. 762-773 - James H. Tomkinson:
UCAD: Building Design Automation with general purpose software tools on UNIX. 774-787 - Robert A. Walker, Donald E. Thomas:
Behavioral level transformation in the CMU-DA system. 788-789 - Shmuel Wimer, N. Sharfman:
HOPLA-PLA optimization and synthesis. 790-794 - Samuel Chuquillanqui:
Internal connection problem in large optimized PLAs. 795-802 - Adam Pawlak:
Microprocessor systems modeling with MODLAN. 804-811
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-08 01:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
