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ORCIDAntonio J. Acosta 0001
Antonio Acosta-Jimenez – Antonio Acosta-Jiménez
Person information
- affiliation: University of Sevilla, Spain
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2020 – today
- 2024
[c40]Luis F. Rojas-Muñoz
, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Eros Camacho-Ruiz, Pablo Navarro-Torrero, Apurba Karmakar, Carlos Fernández García, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Alejandro Casado-Galán, Pau Ortega-Castro, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández, Piedad Brox:
Cryptographic Security Through a Hardware Root of Trust. ARC 2024: 106-119- 2023
- [c39]Virginia Zúñiga-González, Erica Tena-Sánchez, Antonio J. Acosta:
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks. DCIS 2023: 1-6 - 2022
- [j21]Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Antonio J. Acosta, Carlos Jesús Jiménez-Fernández, Ricardo Chaves:
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher. IEEE Access 10: 65548-65561 (2022) - [j20]Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embed. Syst. Lett. 14(2): 99-102 (2022) - 2021
- [j19]Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta:
Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. IEEE Trans. Emerg. Top. Comput. 9(2): 787-796 (2021) - 2020
- [j18]Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta:
Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. ACM J. Emerg. Technol. Comput. Syst. 16(3): 30:1-30:16 (2020) - [c38]Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández:
Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j17]Erica Tena-Sánchez, Antonio J. Acosta:
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks. Int. J. Circuit Theory Appl. 47(2): 238-253 (2019) - 2018
- [c37]Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta:
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. DCIS 2018: 1-6 - [c36]Erica Tena-Sánchez, Antonio J. Acosta:
Effect of Temperature Variation in Experimental DPA and DEMA Attacks. PATMOS 2018: 163-168 - 2017
- [j16]Antonio J. Acosta, Tommaso Addabbo:
Guest Editorial "Secure lightweight crypto-hardware". Int. J. Circuit Theory Appl. 45(2): 143-144 (2017) - [j15]Antonio J. Acosta, Tommaso Addabbo, Erica Tena-Sánchez:
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview. Int. J. Circuit Theory Appl. 45(2): 145-169 (2017) - [j14]Antonio J. Acosta, Erica Tena-Sánchez, Carlos Jesús Jiménez-Fernández, Javier M. Mora-Merchan:
Power and Energy Issues on Lightweight Cryptography. J. Low Power Electron. 13(3): 326-337 (2017) - 2016
- [j13]Piedad Brox, Macarena C. Martínez-Rodríguez, Erica Tena-Sánchez, Iluminada Baturone, Antonio J. Acosta:
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions. Int. J. Circuit Theory Appl. 44(1): 4-20 (2016) - [c35]Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez:
Secure cryptographic hardware implementation issues for high-performance applications. PATMOS 2016: 76-83 - 2015
- [c34]Macarena C. Martínez-Rodríguez, Piedad Brox, Erica Tena, Antonio J. Acosta, Iluminada Baturone:
Programmable ASICs for model predictive control. ICIT 2015: 1593-1598 - [c33]Erica Tena-Sánchez, Antonio J. Acosta:
DPA vulnerability analysis on Trivium stream cipher using an optimized power model. ISCAS 2015: 1846-1849 - 2014
- [j12]Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2): 203-215 (2014) - [c32]Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
Low-Power Differential Logic Gates for DPA Resistant Circuits. DSD 2014: 671-674 - [c31]Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta:
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications. PATMOS 2014: 1-8 - 2013
- [j11]Piedad Brox, Javier Castro-Ramirez, Macarena C. Martínez-Rodríguez, Erica Tena, Carlos Jesús Jiménez-Fernández, Iluminada Baturone, Antonio J. Acosta:
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3182-3194 (2013) - 2012
- [j10]Luis A. Camuñas-Mesa, Carlos Zamarreño-Ramos, Alejandro Linares-Barranco, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors. IEEE J. Solid State Circuits 47(2): 504-517 (2012) - [c30]Macarena C. Martínez-Rodríguez, Piedad Brox, Javier Castro-Ramirez, Erica Tena, Antonio J. Acosta, Iluminada Baturone:
ASIC-in-the-loop methodology for verification of piecewise affine controllers. ICECS 2012: 388-391 - 2011
- [j9]Luis A. Camuñas-Mesa, Antonio Acosta-Jimenez, Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 777-790 (2011) - 2010
- [c29]Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta:
Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS 2010: 3220-3223
2000 – 2009
- 2009
- [j8]Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco, Rafael Paz-Vicente, Francisco Gomez-Rodriguez, Luis A. Camuñas-Mesa, Raphael Berner, Manuel Rivas Pérez, Tobi Delbrück, Shih-Chii Liu, Rodney J. Douglas, Philipp Häfliger, Gabriel Jiménez-Moreno, Antón Civit Balcells, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Bernabé Linares-Barranco:
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-Processing- Learning-Actuating System for High-Speed Visual Object Recognition and Tracking. IEEE Trans. Neural Networks 20(9): 1417-1438 (2009) - [c28]Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS 2009: 76-85 - 2008
- [j7]Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Carmen Serrano-Gotarredona, José Antonio Pérez-Carrasco, Bernabé Linares-Barranco, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit Balcells:
On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing. IEEE Trans. Neural Networks 19(7): 1196-1219 (2008) - [c27]Antonio Jose Ginés, Ricardo Doldán, Alberto Villegas, Antonio J. Acosta, Maria Angeles Jalón, Diego Vázquez, Adoración Rueda, Eduardo J. Peralías:
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS 2008: 1252-1255 - [c26]Luis A. Camuñas-Mesa, Antonio Acosta-Jimenez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Fully digital AER convolution chip for vision processing. ISCAS 2008: 652-655 - 2007
- [c25]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD 2007: 156-159 - [c24]Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit Balcells, Bernabé Linares-Barranco:
Spike Events Processing for Vision Systems. ISCAS 2007: 841-844 - [c23]Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta:
Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896 - [c22]Renato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider:
Asynchronous Staggered Set/Reset Techniques for Low-Noise Applications. ISCAS 2007: 1799-1802 - 2006
- [j6]Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Bernabé Linares-Barranco:
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2548-2566 (2006) - [c21]Rafael Serrano-Gotarredona, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Alejandro Linares-Barranco, Rafael Paz-Vicente, Francisco Gomez-Rodriguez:
High-speed image processing with AER-based components. ISCAS 2006 - [c20]Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Bernabé Linares-Barranco:
An arbitrary kernel convolution AER-transceiver chip for real-time image filtering. ISCAS 2006 - [c19]Raúl Jiménez, Pilar Parra Fernández, Javier Castro-Ramirez, Manuel Sanchez-Raya, Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449 - 2005
- [j5]Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero:
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1(1): 11-19 (2005) - [j4]Manuel Delgado-Restituto, Antonio J. Acosta, Ángel Rodríguez-Vázquez:
A mixed-signal integrated circuit for FM-DCSK modulation. IEEE J. Solid State Circuits 40(7): 1460-1471 (2005) - [c18]Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco, Rafael Paz-Vicente, Francisco Gomez-Rodriguez, Håvard Kolle Riis, Tobi Delbrück, Shih-Chii Liu, S. Zahnd, Adrian M. Whatley, Rodney J. Douglas, Philipp Häfliger, Gabriel Jiménez-Moreno, Antón Civit, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Bernabé Linares-Barranco:
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems. NIPS 2005: 1217-1224 - 2003
- [c17]Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS 2003: 491-500 - 2002
- [c16]Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta:
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS 2002: 209-218 - [c15]Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero:
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457 - [e1]Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido:
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002. Lecture Notes in Computer Science 2451, Springer 2002, ISBN 3-540-44143-3 [contents] - 2001
- [c14]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero:
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471 - [c13]Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda:
Analog/mixed-signal IP modeling for design reuse. DATE 2001: 766-767 - [c12]Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486 - 2000
- [c11]Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE 2000: 534-538 - [c10]Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462 - [c9]Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas:
VHDL-based behavioural description of pipeline ADCs. ISCAS 2000: 681-684 - [c8]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158 - [c7]Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda:
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS 2000: 295-305 - [c6]Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero:
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS 2000: 316-326
1990 – 1999
- 1999
- [j3]T. A. García, Antonio J. Acosta, J. M. Mora, J. Ramos, José Luis Huertas:
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. J. Electron. Test. 15(1-2): 115-127 (1999) - 1998
- [c5]Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia:
Efficient self-timed circuits based on weak NMOS-trees. ICECS 1998: 179-182 - [c4]T. A. García, Antonio J. Acosta, José L. Huertas, J. M. Mora, J. Ramos:
Self-Timed Boundary-Scan Cells for Multi-Chip Module Test. VTS 1998: 92-97 - 1995
- [j2]Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas:
SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits 30(7): 835-838 (1995) - [j1]Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano:
Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers 44(12): 1456-1461 (1995) - [c3]Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas:
New CMOS VLSI linear self-timed architectures. ASYNC 1995: 14-23 - 1993
- [c2]Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas:
Modeling of real bistables in VHDL. EURO-DAC 1993: 460-465 - [c1]Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro:
A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS 1993: 2019-2022
Coauthor Index
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