"Inertial and degradation delay model for CMOS logic gates."

Jorge Juan-Chico et al. (2000)

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DOI: 10.1109/ISCAS.2000.857130

access: closed

type: Conference or Workshop Paper

metadata version: 2022-07-11

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Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462

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