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Journal Articles
- 2023
[j9]Charles Augustine
, Hai Helen Li:
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19. IEEE Des. Test 40(1): 105-107 (2023)- [j8]Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das:
Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers 72(6): 1539-1553 (2023) - 2020
- [j7]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. IEEE J. Solid State Circuits 55(4): 977-987 (2020) - 2019
- [j6]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - 2017
- [j5]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52(1): 50-63 (2017) - 2016
- [j4]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - [j3]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51(1): 117-129 (2016) - [j2]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65(4): 1010-1024 (2016) - 2013
- [j1]Niladri Narayan Mojumder, Xuanyao Fong, Charles Augustine, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy:
Dual pillar spin-transfer torque MRAMs for low power applications. ACM J. Emerg. Technol. Comput. Syst. 9(2): 14:1-14:17 (2013)
Conference and Workshop Papers
- 2023
- [c35]Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De:
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c34]Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM 2021: 88-96 - [c33]Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das:
Cache Compression with Efficient in-SRAM Data Comparison. NAS 2021: 1-8 - [c32]Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid, A. Raman, K. Subramanian, Feroze Merchant, James W. Tschanz, Muhammad M. Khellah:
All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits 2021: 1-2 - 2020
- [c31]Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC 2020: 380-382 - [c30]Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De:
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits 2020: 1-2 - [c29]Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De:
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [c28]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De:
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2 - 2019
- [c27]Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das:
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA 2019: 81-93 - [c26]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. VLSI Circuits 2019: 124- - 2018
- [c25]Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs:
Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. BioCAS 2018: 1-4 - [c24]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - 2017
- [c23]Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis:
Event-driven random backpropagation: Enabling neuromorphic deep learning machines. ISCAS 2017: 1-4 - 2016
- [c22]Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs:
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. BioCAS 2016: 164-167 - [c21]Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs:
Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS 2016: 580-583 - [c20]Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci:
Synaptic sampling in hardware spiking neural networks. ISCAS 2016: 2090-2093 - [c19]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC 2016: 152-153 - 2015
- [c18]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - [c17]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC 2015: 1-3 - 2014
- [c16]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - 2013
- [c15]Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz:
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED 2013: 181-186 - 2012
- [c14]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Cognitive computing with spin-based neural networks. DAC 2012: 1262-1263 - [c13]Georgios Panagopoulos, Charles Augustine, Kaushik Roy:
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE 2012: 1443-1446 - [c12]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Spin based neuron-synapse module for ultra low power programmable computational networks. IJCNN 2012: 1-7 - [c11]Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED 2012: 185-190 - [c10]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Ultra low energy analog image processing using spin based neurons. NANOARCH 2012: 211-217 - 2011
- [c9]Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan:
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH 2011: 122-128 - [c8]Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Kaushik Roy:
Low-power functionality enhanced computation architecture using spin-based devices. NANOARCH 2011: 129-136 - 2010
- [c7]Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy:
Data-dependant sense-amplifier flip-flop for low power applications. CICC 2010: 1-4 - [c6]Georgios Karakonstantis, Charles Augustine, Kaushik Roy:
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS 2010: 3-8 - 2009
- [c5]Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy:
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC 2009: 847-852 - [c4]Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy:
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED 2009: 80-85 - 2008
- [c3]Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy:
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC 2008: 278-283 - [c2]Nilanjan Banerjee, Charles Augustine, Kaushik Roy:
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT 2008: 323-331 - 1992
- [c1]Louise Osterholtz, Charles Augustine, Arthur E. McNair, Ivica Rogina, Hiroaki Saito, Tilo Sloboda, Joe Tebelskis, Alex Waibel:
Testing generality in JANUS: a multi-lingual speech translation system. ICASSP 1992: 209-212
Editorship
- 2022
- [e1]Hai Helen Li, Charles Augustine, Ayse Kivilcim Coskun, Swaroop Ghosh:
ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022. ACM 2022, ISBN 978-1-4503-9354-6 [contents]
Informal and Other Publications
- 2017
- [i5]Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs:
Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection. CoRR abs/1701.01495 (2017) - [i4]Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci:
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. CoRR abs/1709.10205 (2017) - 2016
- [i3]Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs:
Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR abs/1607.03070 (2016) - [i2]Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis:
Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. CoRR abs/1612.05596 (2016) - 2012
- [i1]Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy:
Proposal For Neuromorphic Hardware Using Spin Devices. CoRR abs/1206.3227 (2012)
Coauthor Index
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