"Cache Design with Domain Wall Memory."

Rangharajan Venkatesan et al. (2016)

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DOI: 10.1109/TC.2015.2506581

access: closed

type: Journal Article

metadata version: 2021-10-14

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  - https://dblp.org/rec/journals/tc/VenkatesanKSARR16
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan:
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65(4): 1010-1024 (2016)

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