default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMaria J. Avedillo
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
Journal Articles
- 2023
[j19]Maria J. Avedillo
, Manuel Jiménez Través, Corentin Delacour, Aida Todri-Sanial, Bernabé Linares-Barranco, Juan Núñez:
Operating Coupled VO₂-Based Oscillators for Solving Ising Models. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 901-913 (2023)- [j18]Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Effect of Device Mismatches in Differential Oscillatory Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 872-883 (2023) - 2022
- [j17]Aida Todri-Sanial, Stefania Carapezzi, Corentin Delacour, Madeleine Abernot, Thierry Gil, Elisabetta Corti, Siegfried F. Karg, Juan Núñez, Manuel Jiménez Través, Maria J. Avedillo, Bernabé Linares-Barranco:
How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Trans. Neural Networks Learn. Syst. 33(5): 1996-2009 (2022) - 2021
- [j16]Juan Núñez, José M. Quintana, Maria José Avedillo, Manuel Jiménez Través, Aida Todri-Sanial, Elisabetta Corti, Siegfried F. Karg, Bernabé Linares-Barranco:
Insights Into the Dynamics of Coupled VO2 Oscillators for ONNs. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3356-3360 (2021) - 2019
- [j15]Juan Núñez, Maria J. Avedillo:
Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access 7: 6724-6732 (2019) - 2018
- [j14]Maria J. Avedillo, Juan Núñez:
Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Int. J. Circuit Theory Appl. 46(3): 647-655 (2018) - 2014
- [j13]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2238-2242 (2014) - 2013
- [j12]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. 44(9): 807-813 (2013) - 2009
- [j11]José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi:
Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 350-363 (2009) - 2008
- [j10]Héctor Pettenghi, Maria J. Avedillo, José M. Quintana:
Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectron. J. 39(2): 241-247 (2008) - 2006
- [j9]Maria J. Avedillo, José M. Quintana, Héctor Pettenghi Roldán:
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 334-338 (2006) - 2005
- [j8]José M. Quintana, Maria J. Avedillo:
Analysis of frequency divider RTD circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2234-2247 (2005) - 2004
- [j7]Maria J. Avedillo, José M. Quintana, Raúl Jiménez-Naharro:
Pass-transistor based implementations of threshold logic gates for WOS filtering. Microelectron. J. 35(11): 869-873 (2004) - [j6]Maria J. Avedillo, José M. Quintana, Hamid El Alami, Antonio Jiménez-Calderón:
A Practical Parallel Architecture for Stacks Filters. J. VLSI Signal Process. 38(2): 91-100 (2004) - 2003
- [j5]Valeriu Beiu, José M. Quintana, Maria J. Avedillo:
VLSI implementations of threshold logic-a comprehensive survey. IEEE Trans. Neural Networks 14(5): 1217-1243 (2003) - 2002
- [j4]Manuel Martínez, Maria José Avedillo, José M. Quintana, José Luis Huertas:
COPAS: A New Algorithm for the Partial Input Encoding Problem. VLSI Design 14(2): 171-181 (2002) - 2001
- [j3]José M. Quintana, Maria J. Avedillo, José Luis Huertas:
Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electron. Test. 17(1): 69-73 (2001) - 2000
- [j2]Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
νMOS-based Sorter for Arithmetic Applications. VLSI Design 11(2): 129-136 (2000) - 1995
- [j1]Maria J. Avedillo, José M. Quintana, José Luis Huertas:
Constrained state assignment of easily testable FSMs. J. Electron. Test. 6(1): 133-138 (1995)
Conference and Workshop Papers
- 2023
- [c53]Juan Núñez, Maria J. Avedillo, Manuel Jiménez Través:
Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. SMACD 2023: 1-4 - 2022
- [c52]Manuel Jiménez Través, Maria José Avedillo, Juan Núñez, Bernabé Linares-Barranco:
Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. DCIS 2022: 1-5 - [c51]Juan Núñez, Simon Thomann, Hussam Amrouch, Maria J. Avedillo:
Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. ICECS 2022 2022: 1-4 - [c50]Madeleine Abernot, Thierry Gil, Evgenii Kurylin, Tanguy Hardelin, Alexandre Magueresse, Théophile Gonos, Manuel Jiménez Través, Maria José Avedillo, Aida Todri-Sanial:
Oscillatory Neural Networks for Obstacle Avoidance on Mobile Surveillance Robot E4. IJCNN 2022: 1-8 - 2020
- [c49]Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Oscillatory Hebbian Rule (OHR): An adaption of the Hebbian rule to Oscillatory Neural Networks. DCIS 2020: 1-6 - [c48]Manuel Jiménez Través, Juan Núñez, Maria José Avedillo:
An Approach to the Device-Circuit Co-Design of HyperFET Circuits. ISCAS 2020: 1-5 - 2018
- [c47]Hector J. Quintero, Manuel Jiménez Través, Maria J. Avedillo, Juan Núñez:
Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. SMACD 2018: 81-84 - 2017
- [c46]Juan Núñez, Maria J. Avedillo:
Exploring logic architectures suitable for TFETs devices. ISCAS 2017: 1-4 - 2016
- [c45]Maria J. Avedillo, Juan Núñez:
Impact of pipeline in the power performance of tunnel transistor circuits. PATMOS 2016: 256-261 - 2014
- [c44]Juan Núñez, Maria J. Avedillo, Hector J. Quintero:
DOE based high-performance gate-level pipelines. PATMOS 2014: 1-4 - 2013
- [c43]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD 2013: 280-283 - 2012
- [c42]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS 2012: 480-483 - [c41]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS 2012: 437-442 - [c40]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS 2012: 166-174 - 2011
- [c39]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI 2011: 387-390 - 2010
- [c38]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Evaluation of RTD-CMOS Logic Gates. DSD 2010: 621-627 - [c37]Juan Núñez, Maria J. Avedillo, José M. Quintana:
Single phase MOS-NDR mobile networks. ISCAS 2010: 153-156 - [c36]Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo:
An improved RNS generator 2n +/- k based on threshold logic. VLSI-SoC 2010: 119-124 - 2009
- [c35]Juan Núñez, José M. Quintana, Maria J. Avedillo:
Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS 2009: 1811-1814 - 2008
- [c34]José M. Quintana, Maria J. Avedillo:
Analysis of the critical rise time in MOBILE-based circuits. ICECS 2008: 938-941 - [c33]Juan Núñez, José M. Quintana, Maria J. Avedillo:
Limits to a correct operation in RTD-based ternary inverters. ISCAS 2008: 604-607 - [c32]Héctor Pettenghi, Maria J. Avedillo, José M. Quintana:
A novel contribution to the RTD-based threshold logic family. ISCAS 2008: 2350-2353 - 2007
- [c31]Juan Núñez, José M. Quintana, Maria J. Avedillo:
Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD 2007: 930-933 - [c30]Juan Núñez, José M. Quintana, Maria J. Avedillo:
Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI 2007: 114-119 - [c29]Héctor Pettenghi, Maria J. Avedillo, José M. Quintana:
Non Return Mobile Logic Family. ISCAS 2007: 125-128 - [c28]Juan Núñez, José M. Quintana, Maria J. Avedillo:
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL 2007: 51 - [c27]Juan Núñez, José M. Quintana, Maria J. Avedillo:
A quasi-differential quantizer based on SMOBILE. SBCCI 2007: 251-256 - 2006
- [c26]José M. Quintana, Maria J. Avedillo, Juan Núñez:
Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD 2006: 530-536 - [c25]Juan Núñez, José M. Quintana, Maria José Avedillo:
Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS 2006: 403-406 - [c24]David Bol, Jean-Didier Legat, José M. Quintana, Maria José Avedillo:
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS 2006: 1049-1052 - [c23]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Self-latching operation limits for MOBILE circuits. ISCAS 2006 - 2005
- [c22]Maria J. Avedillo, José M. Quintana, Héctor Pettenghi:
Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP 2005: 254-259 - [c21]Maria J. Avedillo, José M. Quintana, José L. Huertas:
Robust frequency divider based on resonant tunneling devices. ISCAS (3) 2005: 2647-2650 - 2004
- [c20]Maria J. Avedillo, José M. Quintana:
A Threshold Logic Synthesis Tool for RTD Circuits. DSD 2004: 624-627 - [c19]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Programmable logic gate based on resonant tunnelling devices. ISCAS (3) 2004: 697-700 - 2003
- [c18]Valeriu Beiu, Maria J. Avedillo, José M. Quintana:
Review of Capacitive Threshold Gate Implementations. ICANN 2003: 737-744 - [c17]Valeriu Beiu, José M. Quintana, Maria J. Avedillo:
Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence 2003: 44-49 - 2002
- [c16]Manuel Martínez, Maria J. Avedillo, José M. Quintana, H. Süß, Manfred Koegst:
An Encoding Technique for Low Power CMOS Implementations of Controllers. DATE 2002: 1083 - [c15]José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda:
Threshold-logic-based design of compressors. ICECS 2002: 661-664 - [c14]Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda:
High-speed low-power logic gates using floating gates. ISCAS (5) 2002: 389-392 - [c13]José M. Quintana, Maria J. Avedillo, José L. Huertas:
Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) 2002: 599-602 - [c12]Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas:
Simple parallel weighted order statistic filter implementations. ISCAS (4) 2002: 607-610 - 2001
- [c11]Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo:
Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD 2001: 94-101 - [c10]José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
Practical low-cost CPL implementations threshold logic functions. ACM Great Lakes Symposium on VLSI 2001: 139-144 - [c9]José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
Low-power logic styles for full-adder circuits. ICECS 2001: 1417-1420 - [c8]José M. Quintana, Maria J. Avedillo:
Reed-Muller descriptions of symmetric functions. ISCAS (4) 2001: 682-685 - 2000
- [c7]José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda:
Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. SBCCI 2000: 321-326 - 1999
- [c6]Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE 1999: 521-525 - [c5]Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
vMOS-based sorters for multiplier implementations. ISCAS (1) 1999: 338-341 - 1998
- [c4]Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
A Dynamic Model for the State Assignment Problem. DATE 1998: 835-839 - 1995
- [c3]José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas:
Optimum PLA folding through boolean satisfiability. ASP-DAC 1995 - 1993
- [c2]Maria J. Avedillo, José M. Quintana, José L. Huertas:
Easily Testable PLA-based FSMS. ISCAS 1993: 1603-1606 - 1990
- [c1]Maria J. Avedillo, José M. Quintana, José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC 1990: 552-556
Informal and Other Publications
- 2022
- [i1]Jafar Shamsi, Maria José Avedillo, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
Effect of Device Mismatches in Differential Oscillatory Neural Networks. CoRR abs/2211.05497 (2022)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-05-08 21:42 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
