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ORCIDDSD 2001: Warsaw, Poland
- Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland. IEEE Computer Society 2001, ISBN 0-7695-1239-9
System Design
- Kjell Torkelsson, Johan Ditmar:
Header Compression in Handel-C - An Internet Application and a New Design Language. 2-7 - George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos:
A Multi-Lingual Synthesis and Verification Environment. 8-15 - Volker Aue, Johannes Kneip, Matthias Weiss, Michael Bolle, Gerhard P. Fettweis:
A Design Methodology for High Performance IC's: Wireless Broadband Radio Baseband Case Study. 16-20 - Juha-Pekka Soininen, Sandrine Boumard
, Tommi Salminen, Hannu Heusala:
Application of Decision-Making Method for Architecture Selection of ADSL Modem. 21-29
Logic Synthesis
- Lech Józwiak, Artur Chojnacki:
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. 30-37 - Mariusz Rawski, Rafal Rzechowski, Zbigniew Jachna, Ireneusz Brzozowski:
Practical Aspects of Logic Synthesis Based on Functional Decomposition. 38-45 - Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk:
Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. 46-53 - Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther:
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. 54-61
Embedded Systems
- Rolf Ernst:
Combining Languages in Embedded System Design. 62 - Luis Alejandro Cortés, Petru Eles, Zebo Peng:
Hierarchical Modeling and Verification of Embedded Systems. 63-71
Decision Diagrams and Synthesis
- Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler:
Minimization of OPKFDDs Using Genetic Algorithms. 72-78 - Pawel Kerntopf:
An Approach to Minimization of Decision Diagrams . 79-86 - Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky:
Synthesis of ASM-based Self-Checking Controllers. 87-93 - Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo:
Two-Criterial Constraint-Driven FSM State Encoding for Low Power. 94-101
Reconfigurable Computing
- Steven A. Guccione:
Reconfigurable Computing at Xilinx. 102 - Reiner W. Hartenstein:
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. 103-111
Reconfigurable Computing
- Iouliia Skliarova, António de Brito Ferrari:
Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations. 112-119 - Claudia Feregrino Uribe, S. R. Jones:
Optimisation of PPMC Model for Hardware Implementation. 120-126 - Ernesto Martins, José Alberto Fonseca:
Traffic Scheduling Coprocessor with Schedulability Analysis Capability. 127-134 - L. Bubb, Martyn Edwards, Peter Green, C. Pimlott, K. Rees, M. Stewart, A. Taylor, M. Vakondios, J. Yates:
A Run-Time Support Environment for Reconfigurable Systems. 135-143
Synthesis and Verification Posters
- Muthukumar Venkatesan:
An Improved Input-Output Encoding Approach for Functional Decomposition. 144-147 - Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst:
Level Assignment for Displaying Combinational Logic. 148-151 - Wiktor B. Daszczuk, Waldemar Grabski, Jerzy Miescicki, Jacek Wytrebowicz:
System Modeling in the COSMA Environment. 152-157 - Wiktor B. Daszczuk:
Evaluation of Temporal Formulas Based on "Checking by Spheres". 158-164 - Christian Stangier, Ulrich Holtmann:
Applying Formal Verification with Protocol Compiler. 165-169 - Valeri Solovjev:
Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines. 170-177
Panel: Reconfigurable Computing
Processor Design
- Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan:
Dynamic Branch Prediction Using Neural Networks. 178-185 - Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan:
Applying Caching to Two-Level Adaptive Branch Prediction. 186-193 - Janusz Sosnowski, Rafal Jurkiewicz, J. Nowicki:
Experimental Evaluation of CPU Performance Features. 194-201 - Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III:
A Comparison of Five Different Multiprocessor SoC Bus Architectures. 202-211
Synthesis and Test
- Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss:
A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines. 212-219 - Krzysztof Kuchcinski, Christophe Wolinski:
Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming. 220-227 - Vladimir Hahanov, Anna Babich:
Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices. 228-235 - Pawel Tomaszewicz, Mariusz Rawski:
Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments. 236-243
Reversible Logic
- Marek A. Perkowski, Pawel Kerntopf:
Fundamentals of Reversible Logic and Computing. 244 - Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola:
Regular Realization of Symmetric Functions Using Reversible Logic. 245-253
Specialised Architectures
- Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif:
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. 254-261 - José-Alejandro Piñeiro, Javier D. Bruguera, Jean-Michel Muller:
FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation. 262-269 - Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido:
Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques. 270-275 - Oswaldo Cadenas, Graham M. Megson:
Pipelining Considerations for an FPGA Case. 276-285
Synthesis
- Agnieszka Konczykowska:
Very High (Over 40 Gb/s) Speed Circuits for Optical Communications - Design Methodolgy and Application Examples. 286-291 - Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. 292-299 - Petr Fiser, Jan Hlavicka:
On the Use of Mutations in Boolean Minimization. 300-309
Test and Design for Testability
- Andrzej Krasniewski:
Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. 310-317 - Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng:
Fast Test Cost Calculation for Hybrid BIST in Digital Systems. 318-325 - Simon Leung, Adam Postula, Ahmed Hemani:
Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. 326-335
Processor Design
- Mark G. Arnold:
Design of a Faithful LNS Interpolator. 336-345 - Chichyang Chen, Liang-An Chen, Jih-Ren Cheng:
Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition. 346-353 - Albert A. Liddicoat, Michael J. Flynn:
High-Performance Floating Point Divide. 354-363
Specialised Architectures Posters
- Andrzej Ryszko, Kazimierz Wiatr:
An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation. 364-367 - Giuseppe Coldani, Giovanni Danese, Roberto Gandolfi, P. Ghidetti, Francesco Leporati, Remo Lombardi:
Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis. 368-371 - F. Lesser, Jan de Cuveland, Volker Lindenstruth, C. Reichling, R. Schneider, M. W. Schulz:
A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition. 372-375 - Stefan Lund, Lars Bengtsson:
Synchronizing a High-Speed SIMD Processor Array. 376-381 - Aitor Ibarra, Juan Lanchares, José Ignacio Hidalgo, F. Saenz:
Pipelined Genetic Architecture with Fitness on the Fly. 382-385 - Jacek Marczynski, Daniel Tabak:
A Wireless Interconnection Network for Parallel Processing. 386-389 - Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque:
Improving Single-Thread Fetch Performance on a Multithreaded Processor. 390-395 - Øyvind Strøm, Einar J. Aas:
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. 396-399 - Pramote Kuacharoen, Tankut Akgul, Vincent John Mooney, Vijay K. Madisetti:
Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems. 400-407
Physical Design
- Paul Kartschoke, Stephen F. Geissler:
Timing Driven Wiring on an Advanced Microprocessor. 408-413 - Daniel Eckerbert, Per Larsson-Edefors:
Interconnect-Driven Short-Circuit Power Modeling. 414-421 - Krzysztof S. Berezowski:
Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis. 422-429 - Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
A Global Routing Technique for Wave-Steering Design Methodology. 430-437
Specialised Architectures
- Mikael M. Nordman, Wojciech E. Kozlowski, Olavi Vähämäki:
Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell. 438-445 - Michael C. Miller, Daniel Tabak:
A Multiple Context Reconfigurable Functional Unit. 446-452 - Marek Gorgon, Jaromir Przybylo:
FPGA Based Controller for Heterogeneous Image Processing System. 453-457 - Ernest Jamro, Kazimierz Wiatr:
FPGA Implementation of Addition as a Part of the Convolution. 458-465 - Ernest Jamro, Kazimierz Wiatr:
Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution. 466-474
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