default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDaniel Auvergne
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2000 – 2009
- 2007
[i1]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol. CoRR abs/0710.4760 (2007)- 2006
- [j10]B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1677-1684 (2006) - 2005
- [c33]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645 - 2004
- [c32]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192 - [c31]Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109 - [c30]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118 - [c29]A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert
, Daniel Auvergne:
Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731 - [c28]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848 - 2003
- [j9]Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne:
Design Techniques for EEPROMs Embedded in Portable Systems on Chips. IEEE Des. Test Comput. 20(1): 68-75 (2003) - [c27]B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Continuous representation of the performance of a CMOS library. ESSCIRC 2003: 595-598 - [c26]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69 - [c25]Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne:
Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460 - 2002
- [j8]Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne:
Transition time modeling in deep submicron CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1352-1363 (2002) - [c24]Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne:
Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330 - [c23]Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury:
Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. DATE 2002: 316-321 - [c22]Fabrice Picot, Philippe Coll, Daniel Auvergne:
Crosstalk Measurement Technique for CMOS ICs. PATMOS 2002: 65-70 - [c21]Alexis Landrault, Ludovic Pellier, Alexandre Richard, Christian Jay, Michel Robert, Daniel Auvergne:
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. PATMOS 2002: 156-166 - [c20]Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257 - 2001
- [j7]Nadine Azémard, Daniel Auvergne:
POPS: A tool for delay/power performance optimization. J. Syst. Archit. 47(3-4): 375-382 (2001) - [c19]Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312 - [c18]Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne:
Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335 - [c17]Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne:
Output transition time modeling of CMOS structures. ISCAS (5) 2001: 363-366 - [c16]Nadine Azémard, M. Aline, Daniel Auvergne:
Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378 - 2000
- [c15]Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne:
Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. MTDT 2000: 39-46 - [c14]Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne:
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS 2000: 129-138 - [c13]Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne:
Second Generation Delay Model for Submicron CMOS Process. PATMOS 2000: 159-167
1990 – 1999
- 1999
- [j6]Jean Michel Daga, Daniel Auvergne:
A comprehensive delay macro modeling for submicrometer CMOS logics. IEEE J. Solid State Circuits 34(1): 42-55 (1999) - [c12]S. Cremoux, M. Aline, Nadine Azémard, Daniel Auvergne:
Delay-power performance analysis. ICECS 1999: 1543-1546 - [c11]Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne:
RF Interface Design Using Mixed-Mode Methodology. VLSI 1999: 326-333 - [c10]Fernando Moraes, Michel Robert, Daniel Auvergne:
A Virtual CMOS Library Approach for East Layout Synthesis. VLSI 1999: 415-426 - 1998
- [j5]S. Turgis, Daniel Auvergne:
A novel macromodel for power estimation in CMOS structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1090-1098 (1998) - [c9]Jean Michel Daga, E. Ottaviano, Daniel Auvergne:
Temperature Effect on Delay for Low Voltage Applications. DATE 1998: 680-685 - 1997
- [c8]S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne:
Internal power modelling and minimization in CMOS inverters. ED&TC 1997: 603-608 - 1996
- [j4]Denis Deschacht, Christophe Dabrin, Daniel Auvergne:
Delay propagation effect in transistor gates. IEEE J. Solid State Circuits 31(8): 1184-1189 (1996) - [c7]S. Turgis, Nadine Azémard, Daniel Auvergne:
Design and selection of buffers for minimum power-delay product. ED&TC 1996: 224-229 - 1995
- [c6]Jean Michel Daga, Michel Robert, Daniel Auvergne:
Delay modelling improvement for low voltage applications. EURO-DAC 1995: 216-221 - [c5]S. Turgis, Nadine Azémard, Daniel Auvergne:
Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134 - 1994
- [c4]Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne:
Influence of Locig Block Layout Architecture on FPGA Performance. FPL 1994: 34-44 - 1993
- [j3]Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne:
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1170-1177 (1993) - 1992
- [c3]Nadine Azémard, V. Bonzom, Daniel Auvergne:
P.SIZE: a sizing aid for optimized designs. EURO-DAC 1992: 160-165 - 1991
- [j2]D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne:
TVA: A timing verifier with analytic temporal modelling. Microprocessing and Microprogramming 32(1-5): 637-644 (1991) - [c2]Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert:
Formal sizing rules of CMOS circuits. EURO-DAC 1991: 96-100 - 1990
- [c1]Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne:
Path runner: an accurate and fast timing analyser. EURO-DAC 1990: 529-533
1980 – 1989
- 1985
- [j1]Michel Renovell, Gaston Cambon, Daniel Auvergne:
FSPICE: a tool for fault modelling in MOS circuits. Integr. 3(3): 245-255 (1985)
Coauthor Index
aka: Nadine Azémard-Crestani
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-29 21:23 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
