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ORCIDMTDT 2000: San Jose, CA, USA
- 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA. IEEE Computer Society 2000, ISBN 0-7695-0689-5
Failure Mechanism/Defects
- Ray Haythornthwaite:
Failure Mechanisms in Semiconductor Memory Circuits. 7-13 - Jun Zhao, Fred J. Meyer, Fabrizio Lombardi:
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models. 14-19 - Alvin Jee, Jonathon E. Colburn, V. Swamy Irrinki, Mukesh Puri:
Optimizing Memory Tests by Analyzing Defect Coverage. 20-28
Flash/EEPROM Design
- Rino Micheloni, Matteo Zammattio, Giovanni Campardo, Osama Khouri, Guido Torelli:
Hierarchical Sector Biasing Organization for Flash Memories. 29-33 - Osama Khouri, Rino Micheloni, Stefano Gregori
, Guido Torelli:
Fast Voltage Regulator for Multilevel Flash Memories. 34-38 - Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne:
Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. 39-46
New Ideas
- Ruili Zhang, William C. Black Jr., Marwan M. Hassoun:
Windowed MRAM Sensing Scheme. 47-58
Test and Yield
- Jörg E. Vollrath:
Synchronous Dynamic Memory Test Construction: A Field Approach. 59-64 - Kamal Rajkanan:
Yield Analysis Methodology for Low Defectivity Wafer Fabs. 65-72
Memory Testing and Built-in Self-Test
- Said Hamdioui, Ad J. van de Goor, Mike Rodgers, David Eastwick:
March Tests for Realistic Faults in Two-Port Memories. 73-78 - Khoan Truong:
A Simple Built-In Self Test For Dual Ported SRAMs. 79-84 - Michael Redeker, Markus Rudack, Thomas Lobbe, Dirk Niggemeyer:
Using GLFSRs for Pseudo-Random Memory BIST. 85-94
Memory Design
- Wen-Tsong Shiue:
Optimizing Memory Bandwidth with ILP Based Memory Exploration and Assignment for Low Power Embedded Systems. 95-100 - Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim, Cynthia Mar:
66MHz 2.3M Ternary Dynamic Content Addressable Memory. 101-105 - Christophe Frey, F. Genevaux, C. Issartel, D. Turgis, Jean-Pierre Schoellkopf:
A Low Voltage Embedded Single Port SRAM Generator in a 0.18µm Standard CMOS Process. 106-112
Diagnosis
- Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker:
Diagnostic Testing of Embedded Memories Based on Output Tracing. 113-118 - Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo:
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. 119-124 - Zemo Yang, Samiha Mourad:
Crosstalk in Deep Submicron DRAMs. 125-130
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