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ORCIDMihail Petrov
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2020 – today
- 2020
[c17]Vladimir Valkanov
, Mihail Petrov, Daniel Rusev, Irina Radeva:
Modelling Distributed Fault-Tolerant High Availability Storage Cluster Based on Block-Chain Concepts for Tracking Scientific-Research Progress. IEEE Conf. on Intelligent Systems 2020: 590-595
2000 – 2009
- 2008
- [b1]Mihail Petrov:
System Components and Design for OFDM-Based Broadcasting Receivers. TU Darmstadt, Germany, 2008 - 2007
- [c16]Mihail Petrov, Manfred Glesner:
A Scalable Resampling Architecture. GLOBECOM 2007: 3102-3106 - [c15]Mihail Petrov, Manfred Glesner:
An Efficient Fractional-Rate Interpolation Architecture. GLOBECOM 2007: 4554-4558 - 2005
- [c14]Mihail Petrov, Manfred Glesner:
Optimal FFT Architecture Selection for OFDM Receivers on FPGA. FPT 2005: 313-314 - [c13]Mihail Petrov, Manfred Glesner:
A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA. FPT 2005: 323-324 - [c12]Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects. ISCAS (2) 2005: 1078-1081 - [c11]Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 - 2004
- [c10]Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan:
Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 - [c9]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418 - [c8]Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL 2004: 761-770 - [c7]Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner:
Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) 2004: 721-724 - [c6]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV 2004: 156-164 - [c5]Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner:
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. PATMOS 2004: 819-828 - [c4]Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects. SBCCI 2004: 117-122 - 2003
- [c3]Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek:
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL 2003: 1111-1114 - [c2]Abdulfattah Mohammad Obeid, Alberto García Ortiz, Mihail Petrov, Manfred Glesner:
A multi-path high speed Viterbi decoder. ICECS 2003: 1160-1163 - [c1]Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC 2003: 167-
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