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"FPGA Implementation of High Speed Anti-notch Lattice filter for Exon ..."

Vikas Pathak et al. (2021)

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DOI: 10.1109/ISVLSI51109.2021.00082

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  - conf/isvlsi/PathakNJS21
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Vikas Pathak, Satyasai Jagannath Nanda, Amit Mahesh Joshi, Sitanshu Sekhar Sahu:
FPGA Implementation of High Speed Anti-notch Lattice filter for Exon Region Identification in Eukaryotic Genes. ISVLSI 2021: 418-421

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