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ORCIDChenggang Yan 0002
Person information
- affiliation: Nanjing University of Aeronautics and Astronautics, School of Electronic and Information Engineering, Nanjing, China
- affiliation (PhD 2020): Southeast University, Nanjing, China
Other persons with the same name
- Chenggang Yan — disambiguation page
- Chenggang Yan 0001
![[0000-0003-1204-0512]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-1204-0512")
(aka: Chenggang Clarence Yan) — Hangzhou Dianzi University, School of Automation, Hangzhou, China (and 1 more) - Chenggang Yan 0003 — University of North Carolina at Chapel Hill, NC, USA
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2020 – today
- 2024
[j12]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1004-1017 (2024)- 2023
- [j11]Chenggang Yan, Yuxuan Cui, Ke Chen, Bi Wu, Weiqiang Liu:
Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 189-200 (2023) - [j10]Bi Wu, Haonan Zhu, Ke Chen, Chenggang Yan, Weiqiang Liu:
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2412-2424 (2023) - [j9]Chenggang Yan, Xuan Zhao, Tingting Zhang, Jipeng Ge, Chenghua Wang, Weiqiang Liu:
Design of High Hardware Efficiency Approximate Floating-Point FFT Processor. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4283-4294 (2023) - [c11]Yuxuan Cui, Chenggang Yan, Weiqiang Liu:
High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes. ISCAS 2023: 1-5 - [c10]Haonan Wang, Ke Chen, Chenggang Yan, Bi Wu, Weiqiang Liu:
Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications. MWSCAS 2023: 977-981 - [c9]Wenzhuo Xie, Chenggang Yan, Hanghang Wang, Ke Chen, Bi Wu, Chenghua Wang, Weiqiang Liu:
A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing. MWSCAS 2023: 982-986 - 2022
- [j8]Bi Wu, Zhengkuan Wang, Ke Chen, Chenggang Yan, Weiqiang Liu:
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy. IEEE Trans. Circuits Syst. I Regul. Pap. 69(9): 3655-3665 (2022) - [c8]Jipeng Ge, Chenggang Yan, Xuan Zhao, Ke Chen, Bi Wu, Weiqiang Liu:
An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. APCCAS 2022: 1-5 - [c7]Xuan Zhao, Chenggang Yan, Chenghua Wang, Weiqiang Liu:
Design of Approximate Floating-point FFT with Mantissa Bit-width Adjustment Algorithm. APCCAS 2022: 265-269 - [c6]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. ACM Great Lakes Symposium on VLSI 2022: 243-248 - [c5]Ziying Cui, Ke Chen, Bi Wu, Chenggang Yan, Weiqiang Liu:
An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. ACM Great Lakes Symposium on VLSI 2022: 315-318 - [c4]Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. ICCD 2022: 762-769 - 2021
- [j7]Jie Sun, Xin Ding, Chenggang Yan, Weiqiang Liu:
Background Calibration for Bit Weights in Pipelined ADCs Using Adaptive Dither Windows. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1783-1787 (2021) - [j6]Chenggang Yan, Jie Sun, Weiqiang Liu:
An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 2003-2007 (2021) - [c3]Hu Zhang, Chenghua Wang, Chenggang Yan, Yijun Cui, Chongyan Gu, Máire O'Neill, Weiqiang Liu:
A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function. ISCAS 2021: 1-5 - [c2]Jinhe Du, Ke Chen, Peipei Yin, Chenggang Yan, Weiqiang Liu:
Design of An Approximate FFT Processor Based on Approximate Complex Multipliers. ISVLSI 2021: 308-313 - 2020
- [j5]Chenggang Yan, Jianhui Wu, Jie Sun, Jin Jin, Chen Hu:
A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 455-459 (2020) - [j4]Xin Ding, Chenggang Yan, Xin Li, Jianhui Wu:
A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique. IEEE Trans. Circuits Syst. 67-II(12): 2818-2822 (2020) - [c1]Bo Gao, Xin Li, Chenggang Yan, Jianhui Wu:
Active Noise Shaping SAR ADC Based on ISDM with the 5MHz Bandwidth. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j3]Chenggang Yan, Jianhui Wu, Chen Hu, Xincun Ji:
A low power wide tuning range two stage ring VCO with frequency enhancing. IEICE Electron. Express 16(8): 20190090 (2019) - [j2]Xin Li, Desheng Ding, Chenggang Yan, Jianhui Wu:
A digital-mixing-based method for timing skew estimation in time-interleaved ADCs. Microelectron. J. 91: 46-52 (2019) - 2018
- [j1]Chenggang Yan, Chen Hu:
A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control. J. Circuits Syst. Comput. 27(5): 1850072:1-1850072:14 (2018)
Coauthor Index
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last updated on 2024-07-02 23:20 CEST by the dblp team
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