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Jin-Tai Yan
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Publications
- 2013
- [j16]Zhi-Wei Chen, Jin-Tai Yan:
Routability-constrained multi-bit flip-flop construction for clock power reduction. Integr. 46(3): 290-300 (2013) - [c68]Jin-Tai Yan, Zhi-Wei Chen:
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. ACM Great Lakes Symposium on VLSI 2013: 203-208 - [c67]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained replacement using spare cells for design changes. ACM Great Lakes Symposium on VLSI 2013: 347-348 - [c66]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout redundant wire insertion for fixing min-delay violations. ISCAS 2013: 1720-1723 - 2012
- [j15]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. Integr. 45(3): 341-347 (2012) - [c65]Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen:
Top-down-based symmetrical buffered clock routing. ACM Great Lakes Symposium on VLSI 2012: 75-78 - [c64]Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen:
Density-reduction-oriented layer assignment for rectangle escape routing. ACM Great Lakes Symposium on VLSI 2012: 275-278 - [c63]Jin-Tai Yan, Zhi-Wei Chen:
Post-layout OPE-predicted redundant wire insertion for clock skew minimization. ICCD 2012: 504-505 - [c62]Zhi-Wei Chen, Jin-Tai Yan:
Utilization of multi-bit flip-flops for clock power reduction. ICECS 2012: 677-680 - [c61]Jin-Tai Yan, Chia-Han Kao, Ming-Chien Huang, Zhi-Wei Chen:
Efficient assignment of inter-die signals for die-stacking SiP design. ISCAS 2012: 3254-3257 - [c60]Jin-Tai Yan, Zhi-Wei Chen:
Direction-constrained layer assignment for rectangle escape routing. SoCC 2012: 254-259 - 2011
- [c59]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance. DATE 2011: 449-454 - [c58]Zhi-Wei Chen, Jin-Tai Yan:
Timing-constrained I/O buffer placement for flip-chip designs. DATE 2011: 619-624 - [c57]Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. ACM Great Lakes Symposium on VLSI 2011: 205-210 - [c56]Jin-Tai Yan, Zhi-Wei Chen:
Pre-assignment RDL routing via extraction of maximal net sequence. ICCD 2011: 65-70 - [c55]Jin-Tai Yan, Zhi-Wei Chen:
Obstacle-aware length-matching bus routing. ISPD 2011: 61-68 - [c54]Jin-Tai Yan, Tung-Yen Sung, Zhi-Wei Chen:
Simultaneous escape routing based on routability-driven net ordering. SoCC 2011: 81-86 - 2010
- [c53]Jin-Tai Yan, Kai-Ping Lu, Zhi-Wei Chen:
Routability-driven partitioning-based IO assignment for flip-chip designs. APCCAS 2010: 1075-1078 - [c52]Jin-Tai Yan, Ming-Ching Jhong, Zhi-Wei Chen:
Obstacle-aware longest path using rectangular pattern detouring in routing grids. ASP-DAC 2010: 287-292 - [c51]Jin-Tai Yan, Zhi-Wei Chen:
Two-sided single-detour untangling for bus routing. DAC 2010: 206-211 - [c50]Jin-Tai Yan, Zhi-Wei Chen:
Resource-constrained timing-driven link insertion for critical delay reduction. ACM Great Lakes Symposium on VLSI 2010: 119-122 - [c49]Jin-Tai Yan, Chung-Wei Ke, Zhi-Wei Chen:
Ordered escape routing via routability-driven pin assignment. ACM Great Lakes Symposium on VLSI 2010: 417-422 - [c48]Zhi-Wei Chen, Jin-Tai Yan:
Routability-driven flip-flop merging process for clock power reduction. ICCD 2010: 203-208 - [c47]Jin-Tai Yan, Zhi-Wei Chen:
Low-cost low-power bypassing-based multiplier design. ISCAS 2010: 2338-2341 - [c46]Zhi-Wei Chen, Jin-Tai Yan:
Width-constrained wire sizing for non-tree interconnections. ISCAS 2010: 2586-2589 - [c45]Jin-Tai Yan, Ke-Chyuan Chen, Zhi-Wei Chen:
Routability-driven RDL routing with pin reassignment. SoCC 2010: 133-138 - [c44]Jin-Tai Yan, Yu-Cheng Chang, Zhi-Wei Chen:
Thermal via planning for temperature reduction in 3D ICs. SoCC 2010: 392-395 - 2009
- [c43]Jin-Tai Yan, Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs. ASP-DAC 2009: 588-593 - [c42]Jin-Tai Yan, Zhi-Wei Chen:
RDL pre-assignment routing for flip-chip designs. ACM Great Lakes Symposium on VLSI 2009: 401-404 - [c41]Jin-Tai Yan, Zhi-Wei Chen:
Redundant wire insertion for yield improvement. ACM Great Lakes Symposium on VLSI 2009: 409-412 - [c40]Zhi-Wei Chen, Jin-Tai Yan, Hsing-Lin Ko:
Accurate Transformation-based Timing Analysis for RC Non-tree Circuits. ISCAS 2009: 2942-2945 - [c39]Jin-Tai Yan, Zhi-Wei Chen:
Low-power multiplier design with row and column bypassing. SoCC 2009: 227-230 - 2008
- [c38]Jin-Tai Yan, Zhi-Wei Chen:
Timing-driven multi-layer Steiner tree construction with obstacle avoidance. APCCAS 2008: 1684-1687 - [c37]Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee:
Timing-constrained yield-driven redundant via insertion. APCCAS 2008: 1688-1691 - [c36]Jin-Tai Yan, Zhi-Wei Chen:
Electromigration-aware rectilinear Steiner tree construction for analog circuits. APCCAS 2008: 1692-1695 - [c35]Jin-Tai Yan, Zhi-Wei Chen:
Flexible escape routing for flip-chip designs. ICECS 2008: 352-355 - [c34]Jin-Tai Yan, Zhi-Wei Chen:
Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids. ICECS 2008: 658-661 - [c33]Jin-Tai Yan, Zhi-Wei Chen, Yi-Hsiang Chou, Shun-Hua Lin, Herming Chiueh:
Thermal-driven white space redistribution for block-level floorplans. ICECS 2008: 662-665 - 2007
- [c32]Jin-Tai Yan, Shi-Qin Huang, Zhi-Wei Chen:
Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance. ICECS 2007: 717-720 - [c31]Jin-Tai Yan, Zhi-Wei Chen, Kuen-Ming Lin:
Routability-Driven Track Routing for Coupling Capacitance Reduction. ICECS 2007: 849-852 - [c30]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. ISCAS 2007: 3395-3398 - [c29]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity. SoCC 2007: 295-298 - [c28]Jin-Tai Yan, Bo-Yi Chiang:
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. VLSI Design 2007: 899-906 - 2006
- [c27]Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang:
Width and Timing-Constrained Wire Sizing for Critical Area Minimization. APCCAS 2006: 1276-1279 - [c26]Jin-Tai Yan, Zhi-Wei Chen, Chia-Wei Wu, Ming-Yuen Wu:
Optimal Network Analysis in Hierarchical Power Quad-Grids. APCCAS 2006: 1289-1292 - [c25]Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen:
Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis. ICECS 2006: 874-877 - [c24]Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu:
Area-Driven White Space Distribution for Detailed Floorplan Design. ICECS 2006: 1364-1367 - [c23]Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee:
Timing-constrained yield-driven wire sizing for critical area minimization. ISCAS 2006 - [c22]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang:
Multilevel timing-constrained full-chip routing in hierarchical quad-grid model. ISCAS 2006 - [c21]Jin-Tai Yan, Kuen-Ming Lin, Yen-Hsiang Chen:
Optimal shielding insertion for inductive noise avoidance. ISCAS 2006 - [c20]Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo:
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. ISCAS 2006 - [c19]Jin-Tai Yan, Chia-Fang Lee, Yen-Hsiang Chen:
Dynamic Tree Reconstruction with Application to Timing-Constrained Congestion-Driven Global Routing. VLSI Design 2006: 147-152 - 2005
- [j11]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee:
Timing-Constrained Flexibility-Driven Routing Tree Construction. IEICE Trans. Inf. Syst. 88-D(7): 1360-1368 (2005) - [c18]Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo:
LB-packing-based floorplan design on DBL representation. ICECS 2005: 1-4 - [c17]Jin-Tai Yan, Chia-Fang Lee, Tzu-Ya Wang:
Floorplan-aware Steiner tree reconstruction for optimal buffer insertion. ICECS 2005: 1-4 - [c16]Jin-Tai Yan, Yen-Hsiang Chen, Chia-Wei Wu:
Probabilistic congestion prediction in hierarchical quad-grid model. ISCAS (2) 2005: 1350-1353 - [c15]Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen:
Wiring area optimization in floorplan-aware hierarchical power grids. ISCAS (2) 2005: 1366-1369 - [c14]Jin-Tai Yan, Tzu-Ya Wang, Yu-Cheng Lee:
Timing-driven Steiner tree construction based on feasible assignment of hidden Steiner points. ISCAS (2) 2005: 1370-1373 - [c13]Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen:
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. ISCAS (3) 2005: 2219-2222 - 2004
- [c12]Jin-Tai Yan, Shun-Hua Lin:
Timing-constrained congestion-driven global routing. ASP-DAC 2004: 683-686
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