"Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area ..."

Jin-Tai Yan, Bo-Yi Chiang (2007)

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DOI: 10.1109/VLSID.2007.158

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jin-Tai Yan, Bo-Yi Chiang:
Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. VLSI Design 2007: 899-906

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